MC9S12P32CFT Freescale Semiconductor, MC9S12P32CFT Datasheet
MC9S12P32CFT
Specifications of MC9S12P32CFT
Related parts for MC9S12P32CFT
MC9S12P32CFT Summary of contents
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MC9S12P128 Reference Manual Covers also MC9S12P-Family MC9S12P96 MC9S12P64 MC9S12P32 S12 Microcontrollers MC9S12P128RMV1 Rev. 1.13 23 April 2010 freescale.com ...
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To provide the most up-to-date information, the revision of our documents on the World Wide Web will be the most current. Your printed copy may be an earlier revision. To verify you have the latest information available, refer to: http://freescale.com/ ...
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... Serial Peripheral Interface (S12SPIV5 399 Chapter 13 128 KByte Flash Module (S12FTMRC128K1V1 425 Chapter 14 Timer Module (TIM16B8CV2) Block Description . . . . . . . . . . 473 Appendix A Electrical Characteristics 501 Appendix B Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 533 Appendix C Package Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 535 Appendix D Detailed Register Address Map 545 Freescale Semiconductor S12P-Family Reference Manual, Rev. 1.13 3 ...
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... S12P-Family Reference Manual, Rev. 1.13 Freescale Semiconductor ...
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... Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 1.9.1 Chip Configuration Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 1.9.2 Low Power Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 1.10 Security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 1.11 Resets and Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 1.11.1 Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 1.11.2 Interrupt Vectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 1.11.3 Effects of Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 1.12 COP Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 1.13 ATD External Trigger Input Connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Freescale Semiconductor S12P-Family Reference Manual, Rev. 1.13 5 ...
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... PIM Reserved Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 2.3.32 Port M Data Register (PTM 2.3.33 Port M Input Register (PTIM 2.3.34 Port M Data Direction Register (DDRM 2.3.35 Port M Reduced Drive Register (RDRM 2.3.36 Port M Pull Device Enable Register (PERM Chapter 2 S12P-Family Reference Manual, Rev. 1.13 Freescale Semiconductor ...
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... Port Data and Data Direction Register writes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 Memory Map Control (S12PMMCV1) 3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 3.1.1 Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 3.1.2 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 3.1.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 3.1.4 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 3.1.5 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 Freescale Semiconductor Chapter 3 S12P-Family Reference Manual, Rev. 1.13 7 ...
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... Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 5.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 5.3 Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 5.3.1 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 5.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 5.3.3 Family ID Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 8 Chapter 4 Interrupt Module (S12SINTV1) Chapter 5 S12P-Family Reference Manual, Rev. 1.13 Freescale Semiconductor ...
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... State Machine scenarios . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189 6.5.2 Scenario 190 6.5.3 Scenario 190 6.5.4 Scenario 191 6.5.5 Scenario 191 6.5.6 Scenario 192 6.5.7 Scenario 192 6.5.8 Scenario 192 6.5.9 Scenario 193 6.5.10 Scenario 194 6.5.11 Scenario 194 Freescale Semiconductor Chapter 6 S12P-Family Reference Manual, Rev. 1.13 9 ...
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... Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252 8.1.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253 8.1.4 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253 8.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253 8.2.1 RXCAN — CAN Receiver Input Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253 8.2.2 TXCAN — CAN Transmitter Output Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 254 10 Chapter 7 Chapter 8 S12P-Family Reference Manual, Rev. 1.13 Freescale Semiconductor ...
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... External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 330 10.2.1 PWM5 — Pulse Width Modulator Channel 5 Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 330 10.2.2 PWM4 — Pulse Width Modulator Channel 4 Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 330 10.2.3 PWM3 — Pulse Width Modulator Channel 3 Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 330 Freescale Semiconductor Chapter 9 Chapter 10 S12P-Family Reference Manual, Rev. 1.13 ...
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... Initialization/Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 395 11.5.1 Reset Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 395 11.5.2 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 395 11.5.3 Interrupt Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 396 11.5.4 Recovery from Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 398 11.5.5 Recovery from Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 398 Serial Peripheral Interface (S12SPIV5) 12.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 399 12 Chapter 11 Chapter 12 S12P-Family Reference Manual, Rev. 1.13 Freescale Semiconductor ...
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... Security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 470 13.5.1 Unsecuring the MCU using Backdoor Key Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . 470 13.5.2 Unsecuring the MCU in Special Single Chip Mode using BDM . . . . . . . . . . . . . . . . . 471 13.5.3 Mode and Security Effects on Flash Command Availability . . . . . . . . . . . . . . . . . . . . . 472 13.6 Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 472 Freescale Semiconductor Chapter 13 S12P-Family Reference Manual, Rev. 1.13 13 ...
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... A.1.4 Current Injection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 502 A.1.5 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 502 A.1.6 ESD Protection and Latch-up Immunity 503 A.1.7 Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 504 A.1.8 Power Dissipation and Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 505 A.1.9 I/O Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 508 14 Chapter 14 Appendix A Electrical Characteristics S12P-Family Reference Manual, Rev. 1.13 Freescale Semiconductor ...
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... A.11.1 Master Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 529 A.11.2 Slave Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 531 C.1 80 QFP Package Mechanical Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 536 C.2 48 QFN Package Mechanical Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 539 C.3 64 LQFP Package Mechanical Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 542 D.1 Detailed Register Map 545 Freescale Semiconductor Appendix B Ordering Information Appendix C Package Information Appendix D Detailed Register Address Map S12P-Family Reference Manual, Rev ...
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... S12P-Family Reference Manual, Rev. 1.13 Freescale Semiconductor ...
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... MC9S12XS family. In addition to the I/O ports available in each module, further I/O ports are available with interrupt capability allowing wake-up from stop or wait modes. 1.2 Features This section describes the key features of the MC9S12P family. Freescale Semiconductor S12P-Family Reference Manual, Rev. 1.13 17 ...
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... Table 1. MC9S12P Family MC9S12P64 CPU12-V1 64 Kbytes 2 Kbytes 4 Kbytes 16-bit 8-bit 12-bit 3.15 V – 5.5 V Static 80 QFP, 64 LQFP, 48 QFN S12P-Family Reference Manual, Rev. 1.13 MC9S12P96 MC9S12P128 96 Kbytes 128 Kbytes 4 Kbytes 6 Kbytes Yes Yes Yes (1) – 32 MHz Freescale Semiconductor ...
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... ECC (error correction code) bits allow single bit error correction and double fault detection — Erase sector size 256 bytes — Automated program and erase algorithm — User margin level setting for reads Freescale Semiconductor S12P-Family Reference Manual, Rev. 1.13 Device Overview MC9S12P-Family 19 ...
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... System reset generation • Illegal address detection with reset • Low-voltage detection with interrupt or reset • Real time interrupt (RTI) • Computer operating properly (COP) watchdog — Configurable as window COP for enhanced failure detection 20 S12P-Family Reference Manual, Rev. 1.13 Freescale Semiconductor ...
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... Serial Communication Interface Module (SCI) • Full-duplex or single-wire operation • Standard mark/space non-return-to-zero (NRZ) format • Selectable IrDA 1.4 return-to-zero-inverted (RZI) format with programmable pulse widths • 13-bit baud rate selection Freescale Semiconductor S12P-Family Reference Manual, Rev. 1.13 Device Overview MC9S12P-Family 21 ...
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... Low-voltage detect (LVD) with low-voltage interrupt (LVI) • Power-on reset (POR) circuit • Low-voltage reset (LVR) • High temperature sensor 1.3.15 Background Debug (BDM) • Non-intrusive memory access commands • Supports in-circuit programming of on-chip nonvolatile memory 22 S12P-Family Reference Manual, Rev. 1.13 Freescale Semiconductor ...
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... Tagged This matches just before a specific instruction begins execution — Force This is valid on the first instruction boundary after a match occurs • Four trace modes • Four stage state sequencer Freescale Semiconductor S12P-Family Reference Manual, Rev. 1.13 Device Overview MC9S12P-Family 23 ...
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... IOC6 PT6 IOC7 PT7 PWM0 PP0 PWM1 PP1 PWM2 PP2 PWM3 PP3 PWM4 PP4 PWM5 PP5 PP7 PM0 RXCAN PM1 TXCAN PM2 MISO PM3 SS MOSI PM4 SCK PM5 PS0 RXD TXD PS1 PS2 PS3 PJ0 PJ1 PJ2 PJ6 PJ7 Freescale Semiconductor ...
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... Freescale Semiconductor Table 1-2. Device Register Memory Map Module ) PIM (port integration module MMC (memory map control) PIM (port integration module) Reserved MMC (memory map control) ...
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... Table 1-4. Derivatives MC9S12P64 MC9S12P96 64KB 0x3_0000 0x2_8000 0x0C - 0x0F 0x0A - 0x0F 4KB 0x0_3000 S12P-Family Reference Manual, Rev. 1.13 (2) MC9S12P128 96KB 128KB 0x2_0000 0x08 - 0x0F 6KB 0x0_2800 Freescale Semiconductor ...
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... Figure 1-2. MC9S12P-Family Global Memory Map CPU and BDM Local Memory Map 0x0000 REGISTERS 0x0400 D-Flash 0x1400 Unpaged P-Flash RAM 0x4000 Unpaged P-Flash 0x8000 P-Flash window 0xC000 Unpaged P-Flash 0xFFFF Freescale Semiconductor 0x0_0000 RAM_LOW 0x0_4000 0x0_4400 0x0_5400 PF_LOW=0x0_8000 PF_LOW=0x3_0000 PPAGE PF_LOW=0x3_4000 ...
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... It is built from the signal description sections of the individual IP blocks on the device. 28 Table 1-5. Assigned Part ID Numbers Mask Set Number Part ID 0M01N $3980 0M01N $3980 0M01N $3980 0M01N $3980 S12P-Family Reference Manual, Rev. 1.13 Table 1-5 shows the assigned part ID (1) Version ID $FF $FF $FF $FF Freescale Semiconductor ...
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... Device Pinout PWM3/KWP3/PP3 PWM2/KWP2/PP2 PWM1/KWP1/PP1 PWM0/KWP0/PP0 PWM0/IOC0/PT0 IOC1/PT1 IOC2/PT2 IOC3/PT3 KWJ0/PJ0 KWJ1/PJ1 PWM4/IOC4/PT4 API_EXTCLK/PWM5/IOC5/PT5 IOC6/PT6 IOC7/PT7 MODC/BKGD PB0 PB1 PB2 PB3 PB4 Freescale Semiconductor Figure 1-3. MC9S12P-Family 80 QFP pinout MC9S12P-Family QFP Pins shown in BOLD are 14 not available on the 15 64 LQFP package ...
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... Figure 1-4. MC9S12P-Family 64 LQFP pinout MC9S12P-Family 4 64 LQFP Pins shown in BOLD are 12 not available on the 13 48 QFN package S12P-Family Reference Manual, Rev. 1.13 VRH 48 47 VDDA 46 PAD07/AN07 45 PAD06/AN06 44 PAD05/AN05 43 PAD04/AN04 42 PAD03/AN03 41 PAD02/AN02 40 PAD01/AN01 39 PAD00/AN00 38 PAD09/AN09 37 PAD08/AN08 PA3 36 PA2 35 PA1 34 PA0 33 Freescale Semiconductor ...
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... Ports are available for each package option. Routing of pin functions is summarized in Table Table 1-6. Port Availability by Package Option Port AD/ADC Channels Port A pins Port B pins Port E pins inc. IRQ/XIRQ input only Port J Port M Port P Port S Freescale Semiconductor Figure 1-5. MC9S12P-Family 48 QFN pinout MC9S12P-Family 4 48 QFN ...
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... Port 80 QFP 8 64 2/2 PWM0 PWM4 PT0 O PT4 O PT5 1. “O” denotes a possible rerouting under software control S12P-Family Reference Manual, Rev. 1.13 64 LQFP 48 QFN 2/2 2/2 (1) PWM5 O Freescale Semiconductor ...
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Table 1-8. Pin-Out Summary Package Pin Function QFP LQFP QFN 2nd Pin Func PP3 KWP3 PP2 KWP2 PP1 KWP1 PP0 KWP0 PT0 ...
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Table 1-8. Pin-Out Summary Package Pin Function QFP LQFP QFN 2nd Pin Func PB0 — PB1 — PB2 — PB3 — PB4 ...
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Table 1-8. Pin-Out Summary Package Pin Function QFP LQFP QFN 2nd Pin Func XTAL — PJ2 KWJ2 PE3 — PE2 — PE1 ...
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Table 1-8. Pin-Out Summary Package Pin Function QFP LQFP QFN 2nd Pin Func PAD02 AN02 PAD03 AN03 PAD04 AN04 PAD05 AN05 PAD06 ...
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Table 1-8. Pin-Out Summary Package Pin Function QFP LQFP QFN 2nd Pin Func PM4 MOSI PM3 PM2 MISO PM1 TXCAN PM0 ...
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... PE7 — Port E I/O Pin 7 / ECLKX2 PE7 is a general-purpose input or output pin. An internal pull-up is enabled during reset. It can be configured to output ECLKX2. 1.7.3.9 PE[6:5] — Port E I/O Pin 6-5 PE[6:5] are a general-purpose input or output pins. 38 NOTE in all applications. SSX S12P-Family Reference Manual, Rev. 1.13 Freescale Semiconductor ...
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... PM2 / MISO— Port M I/O Pin 3 PM2 is a general-purpose input or output pin. It can be configured as the master input (during master mode) or slave output pin (during slave mode) MISO for the serial peripheral interface (SPI) Freescale Semiconductor S12P-Family Reference Manual, Rev. 1.13 Device Overview MC9S12P-Family ...
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... PT[7:6] are general-purpose input or output pins. They can be configured as timer (TIM) channel 7-6. 1.7.3.29 PT5 / IOC5 / PWM5 / API_EXTCLK — Port T I/O Pin 5 PT5 is a general-purpose input or output pin. It can be configured as timer (TIM) channel 5, pulse width modulator (PWM) output the output of the API_EXTCLK. 40 S12P-Family Reference Manual, Rev. 1.13 Freescale Semiconductor ...
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... These are the power supply and ground input pins for the analog-to-digital converter and the voltage regulator. 1.7.4.5 VRH, VRL — ATD Reference Voltage Input Pins VRH and VRL are the reference voltage input pins for the analog-to-digital converter. Freescale Semiconductor NOTE S12P-Family Reference Manual, Rev. 1.13 Device Overview MC9S12P-Family 41 ...
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... This allows the supply voltage to the PLL to be bypassed independently. Internal power and ground generated by internal regulator. Chapter 7, “S12 Clock, Reset and Power 1.9.2 Low Power Operation. S12P-Family Reference Manual, Rev. 1.13 1.9.1 Chip Configuration Summary. Freescale Semiconductor ...
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... This mode is used for debugging single-chip operation, boot-strapping, or security related operations. The background debug module BDM is active in this mode. The CPU executes a monitor program located in an on-chip ROM. BDM firmware waits for additional serial commands through the BKGD pin. Freescale Semiconductor Table 1-10. Chip Modes Chip Modes ...
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... S12P-Family Reference Manual, Rev. 1.13 CCR Local Enable Mask None None None None None None None None None OSCE Bit in CPMUOSC register None CR[2:0] in CPMUCOP register Wake up Local Enable from STOP None - None - None Yes IRQCR (IRQEN) Yes Freescale Semiconductor Wakeup from WAIT - - Yes Yes ...
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... TCIE, RIE, ILIE) ATDCTL2 (ASCIE) Yes Yes PIEJ0) CPMUINT (OSCIE) No CPMUINT (LOCKIE FCNFG (CCIE) No CANRIER (WUPIE) 8.4.7 Interrupts CANRIER (RXFIE) CANTIER (TXEIE[2:0]) Freescale Semiconductor Wakeup from WAIT Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes ...
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... I bit CPMUAPICTRL (APIE) (API) I bit CPMUHTCL (HTIE) I bit ATDCTL2 (ACMPIE) Reserved — S12P-Family Reference Manual, Rev. 1.13 Wake up Local Enable from STOP Yes No CPMUCTRL (LVIE) No Yes No Yes None - 13.6 Initialization. Freescale Semiconductor Wakeup from WAIT Yes Yes Yes Yes Yes Yes - ...
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... External Trigger Input ETRIG0 ETRIG1 Consult the ATD section for information about the analog-to-digital converter module. References to freeze mode are equivalent to active BDM mode. Freescale Semiconductor Table 1-13 and Table 1-14 Table 1-13. Initial COP Rate Configuration NV[2:0] in CR[2:0] in ...
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... The bandgap reference voltage V connected to the ATD channel SPECIAL17 (see Table 9-15.) using the VSEL (Voltage Access Select Bit) in CPMUHTCTL register (see Table 7-13.) 48 and the output voltage of the temperature sensor V BG S12P-Family Reference Manual, Rev. 1.13 can be HT Freescale Semiconductor ...
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... This section assumes the availability of all features (80-pin package option). Some functions are not available on lower pin count package options. Refer to the pin-out summary section. Freescale Semiconductor Substantial Change(s) Initial version Corrected mistakes in Port J register and field names ...
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... Port Integration Module. If there is more than one function associated with a pin, the priority is indicated by the position in the table from top (highest priority) to bottom (lowest priority). 50 NOTE S12P-Family Reference Manual, Rev. 1.13 Freescale Semiconductor ...
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... GPIO S PS[3:2] GPIO PS1 TXD GPIO PS0 RXD GPIO Freescale Semiconductor Table 2-1. Pin Functions and Priorities I/O Description I MODC input during RESET I/O S12X_BDM communication pin I/O General purpose I/O General purpose O Free-running clock at core clock rate (ECLK x 2) I/O General purpose ...
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... I/O General purpose I ATD analog Table 2-2. Block Memory Map Register S12P-Family Reference Manual, Rev. 1.13 Pin Function after Reset GPIO GPIO GPIO GPIO Access Reset Value Section/Page R/W 0x00 2.3.3/2-63 R/W 0x00 2.3.4/2-63 R/W 0x00 2.3.5/2-64 R/W 0x00 2.3.6/2-64 Freescale Semiconductor ...
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... PERT—Port T Pull Device Enable Register 0x0245 PPST—Port T Polarity Select Register 0x0246 PIM Reserved 0x0247 Port T Routing Register Freescale Semiconductor Table 2-2. Block Memory Map (continued) Register ( S12P-Family Reference Manual, Rev. 1.13 Port Integration Module (S12PPIMV1) Access Reset Value ...
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... R/W 0x00 2.3.35/2-84 R/W 0x00 2.3.36/2-85 R/W 0x00 2.3.37/2-85 R/W 0x00 2.3.38/2-86 R 0x00 2.3.39/2-86 R/W 0x00 2.3.40/2- 2.3.41/2-88 R/W 0x00 2.3.42/2-88 R/W 0x00 2.3.43/2-89 R/W 0x00 2.3.44/2-90 R/W 0x00 2.3.45/2-90 R/W 0x00 2.3.46/2-91 R/W 0x00 2.3.47/2-91 R 0x00 2.3.48/2-92 Freescale Semiconductor ...
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... PB6 PORTB W 0x0002 R DDRA7 DDRA6 DDRA W 0x0003 R DDRB7 DDRB6 DDRB W = Unimplemented or Reserved Freescale Semiconductor Table 2-2. Block Memory Map (continued) Register 5 4 PA5 PA4 PB5 PB4 DDRA5 DDRA4 DDRA3 DDRB5 DDRB4 DDRB3 S12P-Family Reference Manual, Rev. 1.13 Port Integration Module (S12PPIMV1) ...
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... Reserved W = Unimplemented or Reserved PE5 PE4 PE3 DDRE5 DDRE4 DDRE3 Non-PIM Address Range 0 0 PUPEE 0 0 RDPE Non-PIM Address Range DIV16 EDIV4 EDIV3 S12P-Family Reference Manual, Rev. 1. Bit PE1 PE0 PE2 0 0 DDRE2 0 PUPBE PUPAE 0 RDPB RDPA EDIV2 EDIV1 EDIV0 Freescale Semiconductor ...
Page 57
... PTS W 0x0249 PTIS W 0x024A DDRS W 0x024B RDRS W 0x024C PERS W 0x024D PPSS W = Unimplemented or Reserved Freescale Semiconductor Non-PIM Address Range PTT5 PTT4 PTT3 PTIT5 PTIT4 PTIT3 DDRT5 DDRT4 DDRT3 RDRT5 RDRT4 RDRT3 PERT5 PERT4 PERT3 PPST5 PPST4 PPST3 PTTRR5 PTTRR4 0 0 PTS3 0 0 PTIS3 ...
Page 58
... PTM2 PTM1 PTM0 PTIM2 PTIM1 PTIM0 DDRM2 DDRM1 DDRM0 RDRM2 RDRM1 RDRM0 PERM2 PERM1 PERM0 PPSM2 PPSM1 PPSM0 WOMM2 WOMM1 WOMM0 PTP2 PTP1 PTP0 PTIP2 PTIP1 PTIP0 DDRP2 DDRP1 DDRP0 RDRP2 RDRP1 RDRP0 PERP2 PERP1 PERP0 PPSP2 PPSP1 PPSP0 Freescale Semiconductor ...
Page 59
... Reserved W 0x0266 Reserved W 0x0267 Reserved W 0x0268 R PTJ7 PTJ6 PTJ W 0x0269 R PTIJ7 PTIJ6 PTIJ W 0x026A R DDRJ7 DDRJ6 DDRJ W 0x026B R RDRJ7 RDRJ6 RDRJ W 0x026C R PERJ7 PERJ6 PERJ W = Unimplemented or Reserved Freescale Semiconductor PIEP5 PIEP4 PIEP3 PIFP5 PIFP4 PIFP3 S12P-Family Reference Manual, Rev. 1.13 ...
Page 60
... RDR1AD4 RDR1AD3 PER1AD5 PER1AD4 PER1AD3 S12P-Family Reference Manual, Rev. 1. Bit 0 PPSJ2 PPSJ1 PPSJ0 PIEJ2 PIEJ1 PIEJ0 PIFJ2 PIFJ1 PIFJ0 0 PT0AD1 PT0AD0 PT1AD2 PT1AD1 PT1AD0 0 DDR0AD1 DDR0AD0 DDR1AD2 DDR1AD1 DDR1AD0 0 RDR0AD1 RDR0AD0 RDR1AD2 RDR1AD1 RDR1AD0 0 PER0AD1 PER0AD0 PER1AD2 PER1AD1 PER1AD0 Freescale Semiconductor ...
Page 61
... The configuration bit PS is used for two purposes: 1. Configure the sensitive interrupt edge (rising or falling), if interrupt is enabled. 2. Select either a pull-up or pull-down device active. Freescale Semiconductor ...
Page 62
... Disabled Pull Up Disabled Pull Down Disabled Disabled Falling edge Disabled Rising edge Pull Up Falling edge Pull Down Rising edge Disabled Disabled Disabled Disabled Disabled Disabled Disabled Disabled Disabled Falling edge Disabled Rising edge Disabled Falling edge Disabled Rising edge Freescale Semiconductor ...
Page 63
... The associated pin can be used as general purpose I/O. In general purpose output mode the register bit value is driven to the pin. If the associated data direction bit is set read returns the value of the port register bit, otherwise the buffered pin input state is read. Freescale Semiconductor 5 4 PA5 ...
Page 64
... Table 2-6. DDRA Register Field Descriptions Description 5 4 DDRB5 DDRB4 DDRB3 0 0 Table 2-7. DDRB Register Field Descriptions Description S12P-Family Reference Manual, Rev. 1.13 Access: User read/write DDRA2 DDRA1 Access: User read/write DDRB2 DDRB1 Freescale Semiconductor (1) 0 DDRA0 0 (1) 0 DDRB0 0 ...
Page 65
... The associated pin can be used as general purpose I/O. In general purpose output mode the register bit value is driven to the pin. If the associated data direction bit is set read returns the value of the port register bit, otherwise the buffered pin input state is read. Freescale Semiconductor ...
Page 66
... This bit determines whether the associated pin is an input or output. 1 Associated pin is configured as output 0 Associated pin is configured as input 66 Description 5 4 DDRE5 DDRE4 DDRE3 0 0 Table 2-9. DDRE Register Field Descriptions Description S12P-Family Reference Manual, Rev. 1.13 Access: User read/write DDRE2 Freescale Semiconductor ( ...
Page 67
... Port A Pull-up Enable—Enable pull-up devices on all port input pins PUPAE This bit configures whether a pull-up device is activated on all associated port input pins pin is used as output this bit has no effect. 1 Pull-up device enabled 0 Pull-up device disabled Freescale Semiconductor PUPEE 0 1 Table 2-10. PUCR Register Field Descriptions Description S12P-Family Reference Manual, Rev ...
Page 68
... The reduced drive function is independent of which function is being used on a particular pin. 1 Reduced drive selected (approx. 1/5 of the full drive strength) 0 Full drive strength enabled RDPE 0 0 Table 2-11. RDRIV Register Field Descriptions Description S12P-Family Reference Manual, Rev. 1.13 Access: User read/write RDPB Freescale Semiconductor (1) 0 RDPA 0 ...
Page 69
... These bits determine the rate of the free-running clock on the ECLK pin. 00000 ECLK rate = bus clock rate 00001 ECLK rate = bus clock rate divided by 2 00010 ECLK rate = bus clock rate divided by 3,... 11111 ECLK rate = bus clock rate divided by 32 2.3.13 PIM Reserved Register Freescale Semiconductor 5 4 DIV16 EDIV4 0 0 ...
Page 70
... Writing to this register when in special modes can alter the pin functionality Figure 2-11. PIM Reserved Register Figure 2-12. IRQ Control Register (IRQCR) Table 2-13. IRQCR Register Field Descriptions Description S12P-Family Reference Manual, Rev. 1.13 Access: User read Access: User read/write Freescale Semiconductor ( ( ...
Page 71
... Port T Data Register (PTT) Address 0x0240 PTT7 PTT6 W Altern. IOC7 IOC6 Function — — — — Reset Read: Anytime. The data source is depending on the data direction value. Write: Anytime Freescale Semiconductor Figure 2-13. PIM Reserved Register PTT5 PTT4 PTT3 IOC5 IOC4 IOC3 (PWM5) (PWM4) — ...
Page 72
... Read: Anytime Write:Never, writes to this register have no effect. 72 Table 2-14. PTT Register Field Descriptions Description 5 4 PTIT5 PTIT4 PTIT3 Unaffected by reset Figure 2-15. Port T Input Register (PTIT) S12P-Family Reference Manual, Rev. 1.13 Access: User read PTIT2 PTIT1 Freescale Semiconductor (1) 0 PTIT0 u ...
Page 73
... The TIM forces the I/O state output for a timer port associated with an enabled output compare. Else the routed PWM forces the I/O state output for an enabled channel. In these cases the data direction bit will not change. 1 Associated pin is configured as output 0 Associated pin is configured as input Freescale Semiconductor Table 2-15. PTIT Register Field Descriptions Description 5 4 ...
Page 74
... Table 2-17. RDRT Register Field Descriptions Description 5 4 PERT5 PERT4 PERT3 0 0 Table 2-18. PERT Register Field Descriptions Description S12P-Family Reference Manual, Rev. 1.13 Access: User read/write RDRT2 RDRT1 Access: User read/write PERT2 PERT1 Freescale Semiconductor (1) 0 RDRT0 0 (1) 0 PERT0 0 ...
Page 75
... A pull-down device is selected 0 A pull-up device is selected 2.3.22 PIM Reserved Register Address 0x0246 Reset Unimplemented or Reserved 1. Read: Always reads 0x00 Write: Unimplemented Freescale Semiconductor 5 4 PPST5 PPST4 PPST3 0 0 Table 2-19. PPST Register Field Descriptions Description Figure 2-20. PIM Reserved Register S12P-Family Reference Manual, Rev ...
Page 76
... This register controls the routing of PWM channel 0. 1 PWM0 routed to PT0 0 PWM0 routed to PP0 PTTRR5 PTTRR4 PWM5 PWM4 0 0 Figure 2-21. Port T Routing Register (PTTRR) Description S12P-Family Reference Manual, Rev. 1.13 Access: User read — — — Freescale Semiconductor (1) 0 PTTRR0 PWM0 0 ...
Page 77
... The SCI function takes precedence over the general purpose I/O function if enabled. 2.3.25 Port S Input Register (PTIS) Address 0x0249 Reset Unimplemented or Reserved Freescale Semiconductor PTS3 — — Figure 2-22. Port S Data Register (PTS) Table 2-21. PTS Register Field Descriptions Description 5 ...
Page 78
... Associated pin is configured as output 0 Associated pin is configured as input 78 Table 2-22. PTIS Register Field Descriptions Description DDRS3 0 0 Table 2-23. DDRS Register Field Descriptions Description S12P-Family Reference Manual, Rev. 1.13 Access: User read/write DDRS2 DDRS1 Freescale Semiconductor (1) 0 DDRS0 0 ...
Page 79
... PERS This bit controls whether a pull device on the associated port input pin is active pin is used as output this bit has only effect if used in wired-or mode. The polarity is selected by the related polarity select register bit. 1 Pull device enabled 0 Pull device disabled Freescale Semiconductor ...
Page 80
... Output buffer operates as push-pull output Table 2-26. PPSS Register Field Descriptions Description WOMS3 0 0 Table 2-27. WOMS Register Field Descriptions Description S12P-Family Reference Manual, Rev. 1.13 Access: User read/write PPSS3 PPSS2 PPSS1 Access: User read/write WOMS2 WOMS1 Freescale Semiconductor (1) 0 PPSS0 0 (1) 0 WOMS0 0 ...
Page 81
... If the associated data direction bit is set read returns the value of the port register bit, otherwise the buffered pin input state is read. • The SPI function takes precedence over the general purpose I/O function if enabled. Freescale Semiconductor ...
Page 82
... Port M Input Register (PTIM) Address 0x0251 Reset Unimplemented or Reserved 1. Read: Anytime Write:Never, writes to this register have no effect. 82 Description 5 4 PTIM5 PTIM4 PTIM3 Unaffected by reset Figure 2-31. Port M Input Register (PTIM) S12P-Family Reference Manual, Rev. 1.13 Access: User read PTIM2 PTIM1 Freescale Semiconductor (1) 0 PTIM0 u ...
Page 83
... Depending on the configuration of the enabled SPI the I/O state will be forced to be input or output. In this case the data direction bit will not change. 1 Associated pin is configured as output 0 Associated pin is configured as input Freescale Semiconductor Table 2-29. PTIM Register Field Descriptions Description 5 ...
Page 84
... The reduced drive function is independent of which function is being used on a particular pin. 1 Reduced drive selected (approx. 1/5 of the full drive strength) 0 Full drive strength enabled 84 Description 5 4 RDRM5 RDRM4 RDRM3 0 0 Table 2-31. RDRM Register Field Descriptions Description S12P-Family Reference Manual, Rev. 1.13 Access: User read/write RDRM2 RDRM1 Freescale Semiconductor (1) 0 RDRM0 0 ...
Page 85
... Port M pull device select—Configure pull device polarity on input pin PPSM This bit selects a pull- pull-down device if enabled on the associated port input pin. If CAN is active the selection of a pull-down device on the RXCAN input will have no effect pull-down device is selected 0 A pull-up device is selected Freescale Semiconductor 5 4 PERM5 PERM4 PERM3 ...
Page 86
... Read: Always reads 0x00 Write: Unimplemented WOMM5 WOMM4 WOMM3 0 0 Table 2-34. WOMM Register Field Descriptions Description Unaffected by reset Figure 2-37. PIM Reserved Register S12P-Family Reference Manual, Rev. 1.13 Access: User read/write WOMM2 WOMM1 Access: User read Freescale Semiconductor (1) 0 WOMM0 0 ( ...
Page 87
... If the associated data direction bit is set read returns the value of the port register bit, otherwise the buffered pin input state is read. • The PWM function takes precedence over the general purpose I/O function if the related channel is enabled. • Pin interrupts can be generated if enabled in input or output mode. Freescale Semiconductor 5 4 PTP5 ...
Page 88
... Table 2-36. PTIP Register Field Descriptions Description 5 4 DDRP5 DDRP4 DDRP3 0 0 Table 2-37. DDRP Register Field Descriptions Description S12P-Family Reference Manual, Rev. 1.13 Access: User read PTIP3 PTIP2 PTIP1 Access: User read/write DDRP2 DDRP1 Freescale Semiconductor (1) 0 PTIP0 u (1) 0 DDRP0 0 ...
Page 89
... This bit configures the drive strength of the associated output pin as either full or reduced pin is used as input this bit has no effect. The reduced drive function is independent of which function is being used on a particular pin. 1 Reduced drive selected (approx. 1/5 of the full drive strength) 0 Full drive strength enabled Freescale Semiconductor Description 5 4 ...
Page 90
... Table 2-39. PERP Register Field Descriptions Description 5 4 PPSP5 PPSP4 PPSP3 0 0 Table 2-40. PPSP Register Field Descriptions Description S12P-Family Reference Manual, Rev. 1.13 Access: User read/write PPSP2 PPSP1 Access: User read/write PPSP2 PPSP1 Freescale Semiconductor (1) 0 PPSP0 0 (1) 0 PPSP0 0 ...
Page 91
... Writing a logic “1” to the corresponding bit field clears the flag. 1 Active edge on the associated bit has occurred (an interrupt will occur if the associated enable bit is set active edge occurred Freescale Semiconductor 5 4 PIEP5 PIEP4 ...
Page 92
... Pin interrupts can be generated if enabled in input or output mode Unaffected by reset Figure 2-46. PIM Reserved Registers Figure 2-47. Port J Data Register (PTJ) Table 2-43. PTJ Register Field Descriptions Description S12P-Family Reference Manual, Rev. 1.13 Access: User read Access: User read/write PTJ2 PTJ1 Freescale Semiconductor ( (1) 0 PTJ0 0 ...
Page 93
... Read: Anytime Write: Anytime Field 7-6, 2-0 Port J data direction— DDRJ This bit determines whether the associated pin is an input or output. 1 Associated pin is configured as output 0 Associated pin is configured as input Freescale Semiconductor Unaffected by reset Figure 2-48. Port J Input Register (PTIJ) Table 2-44 ...
Page 94
... Pull device enabled 0 Pull device disabled Table 2-46. RDRJ Register Field Descriptions Description Table 2-47. PERJ Register Field Descriptions Description S12P-Family Reference Manual, Rev. 1.13 Access: User read/write RDRJ2 RDRJ1 Access: User read/write PERJ2 PERJ1 Freescale Semiconductor (1) 0 RDRJ0 0 (1) 0 PERJ0 1 ...
Page 95
... Figure 2-53. Port J Interrupt Enable Register (PIEJ) 1. Read: Anytime Write: Anytime Field 7-6, 2-0 Port J interrupt enable— PIEJ This bit enables or disables on the edge sensitive pin interrupt on the associated pin. 1 Interrupt is enabled 0 Interrupt is disabled (interrupt flag masked) Freescale Semiconductor Table 2-48. PPSJ Register Field Descriptions Description 5 ...
Page 96
... Table 2-50. PIFJ Register Field Descriptions Description — — Figure 2-55. Port AD Data Register (PT0AD) Table 2-51. PT0AD Register Field Descriptions Description S12P-Family Reference Manual, Rev. 1.13 Access: User read/write PIFJ2 PIFJ1 Access: User read/write PT0AD1 — — AN9 Freescale Semiconductor (1) 0 PIFJ0 0 (1) 0 PT0AD0 AN8 0 ...
Page 97
... This bit determines whether the associated pin is an input or output. To use the digital input function the ATD Digital Input Enable Register (ATDDIEN) has to be set to logic level “1”. 1 Associated pin is configured as output 0 Associated pin is configured as input Freescale Semiconductor 5 4 PT1AD5 ...
Page 98
... The reduced drive function is independent of which function is being used on a particular pin. 1 Reduced drive selected (approx. 1/5 of the full drive strength) 0 Full drive strength enabled DDR1AD5 DDR1AD4 DDR1AD3 Description Description S12P-Family Reference Manual, Rev. 1.13 Access: User read/write DDR1AD2 DDR1AD1 DDR1AD0 Access: User read/write RDR0AD1 RDR0AD0 Freescale Semiconductor (1) (1) ...
Page 99
... Field 1-0 Port AD pull-up enable—Enable pull-up device on input pin PER0AD This bit controls whether a pull device on the associated port input pin is active pin is used as output this bit has no effect. 1 Pull device enabled 0 Pull device disabled Freescale Semiconductor RDR1AD5 RDR1AD4 RDR1AD3 0 ...
Page 100
... PER1AD5 PER1AD4 PER1AD3 Description Unaffected by reset Figure 2-63. PIM Reserved Registers S12P-Family Reference Manual, Rev. 1.13 Access: User read/write PER1AD2 PER1AD1 PER1AD0 Access: User read (Table 2-59). All Freescale Semiconductor (1) (1) ...
Page 101
... Due to internal synchronization circuits, it can take bus clock cycles until the correct value is read on port data or port input registers, when changing the data direction register. Freescale Semiconductor Table 2-59. Register availability per port Reduced Pull ...
Page 102
... Wired-or mode register (WOMx) If the pin is used as an output this register turns off the active high drive. This allows wired-or type connections of outputs. 102 PTI DDR 0 1 data out output enable module enable S12P-Family Reference Manual, Rev. 1.13 PIN Freescale Semiconductor ...
Page 103
... IRQ will be enabled by setting the IRQEN configuration bit (2.3.14/2-70) and clearing the I-bit in the CPU condition code register inhibited at reset so this pin is initially configured as a simple input with a pull-up. Freescale Semiconductor NOTE S12P-Family Reference Manual, Rev. 1.13 ...
Page 104
... Port J pins PJ[7:6,2:0] can be used for general purpose I/O with pin-interrupt capability. 2.4.3.9 Port AD This port is associated with the ATD. Port AD pins PAD[9:0] can be used for either general purpose I/O, or with the ATD subsystem. 104 S12P-Family Reference Manual, Rev. 1.13 Freescale Semiconductor ...
Page 105
... Valid pulse, interrupt flag set Figure 2-65. Interrupt Glitch Filter on Port P and J (PPS=0) Pulse Ignored Uncertain Valid 1. These values include the spread of the oscillator frequency over temperature, voltage and process. Freescale Semiconductor (Figure 2-66) shorter than a specified time from generating an uncertain t pign t pval Table 2-60 ...
Page 106
... It is not recommended to write PORTx/PTx and DDRx in a word access. When changing the register pins from inputs to outputs, the data may have extra transitions during the write access. Initialize the port data register before enabling the outputs. 106 t pulse Figure 2-66. Pulse Illustration S12P-Family Reference Manual, Rev. 1.13 Freescale Semiconductor ...
Page 107
... Misaligned Bus Access NS SS Unimplemented Address Ranges P-Flash D-Plash NVM IFR Freescale Semiconductor Table 3-1. Revision History Table Table 3-2. Substantial Change(s) Added reserved registers Removed references to the MMCCTL1 register Table 3-3. Glossary Of Terms Address within the CPU12’s Local Address Map Address within the Global Address Map Bus access to an even address ...
Page 108
... S12I devives can be secured to prohibit external access to the on-chip P-Flash. The S12PMMC module determines the access permissions to the on-chip memories in secured and unsecured state. 3.1.5 Block Diagram Figure 3-1 shows a block diagram of the S12PMMC. 108 S12P-Family Reference Manual, Rev. 1.13 Freescale Semiconductor ...
Page 109
... Memory Map and Registers 3.3.1 Module Memory Map A summary of the registers associated with the S12PMMC block is shown in descriptions of the registers and bits are given in the subsections that follow. Freescale Semiconductor Address Decoder & Priority Target Bus Controller P-Flash RAM Figure 3-1. S12PMMC Block Diagram The RESET pin is used the select the MCU’ ...
Page 110
... Reset MODC 0 1. External signal (see Table 3-4). = Unimplemented or Reserved 110 DP14 DP13 DP12 Unimplemented or Reserved Figure 3-2. MMC Register Summary Figure 3-3. Mode Register (MODE) S12P-Family Reference Manual, Rev. 1. DP11 DP10 DP9 PIX3 PIX2 PIX1 Freescale Semiconductor Bit DP8 PIX0 ...
Page 111
... Read: Anytime Write: anytime in special SS, writr-one in NS. This register determines the position of the 256 Byte direct page within the memory map.It is valid for both global and local mapping scheme. Freescale Semiconductor Figure 3-4). Table 3-5. MODE Field Descriptions Description RESET ...
Page 112
... PIX3 S12P-Family Reference Manual, Rev. 1.13 Figure 3-6). Bit0 2 1 PIX2 PIX1 PIX0 Figure 3-8). This supports accessing Freescale Semiconductor 0 ...
Page 113
... MCU Operating Modes • Normal single chip mode This is the operation mode for running application codeThere is no external bus in this mode. • Special single chip mode Freescale Semiconductor Global Address [17:0] Bit14 Bit13 Address [13:0] Address: CPU Local Address Figure 3-8. PPAGE Address Mapping NOTE Table 3-7 ...
Page 114
... However an interrupt service routine can call other routines that are in paged memory. The upper 16KB block of the local CPU memory space (0xC000–0xFFFF) is unpaged recommended that all reset and interrupt vectors point to locations in this area or to the other unmapped pages sections of the local CPU memory map. 114 Instructions). S12P-Family Reference Manual, Rev. 1.13 Freescale Semiconductor ...
Page 115
... CPU is executing a firmware command which uses CPU instructions BDM hardware commands. See the BDM Block Guide for further details. (see Bit17 BDMPPR Register [3:0] Bit17 BDMPPR Register [3:0] Freescale Semiconductor BDM HARDWARE COMMAND Global Address [17:0] Bit14 Bit13 BDM Local Address [13:0] ...
Page 116
... RAM_LOW 0x0_4000 0x0_4400 0x0_5400 0x0_8000 0x3_0000 PPAGE 0x3_4000 0x3_8000 0x3_C000 0x3_FFFF S12P-Family Reference Manual, Rev. 1.13 Global Memory Map REGISTERS Unimplemented Area RAM NVM Resources D-Flash NVM Resources P-Flash 10 *16K paged Unpaged P-Flash Unpaged P-Flash Unpaged P-Flash Unpaged P-Flash Freescale Semiconductor ...
Page 117
... Figure to the unimplemented areas are allowed but the data will be undefined. No misaligned word access from the BDM module will occur; these accesses are blocked in the BDM module (Refer to BDM Block Guide). Freescale Semiconductor Bottom Address 0x0_0000 RAM_LOW = (1) ...
Page 118
... Unpaged P-Flash 0xFFFF Figure 3-11. Implemented Global Address Mapping 118 0x0_0000 RAM_LOW 0x0_4000 0x0_4400 0x0_5400 0x0_8000 PPAGE PF_LOW 0x3_FFFF S12P-Family Reference Manual, Rev. 1.13 Global Memory Map REGISTERS Unimplemented Area RAM NVM Resources D-Flash NVM Resources Unimplemented area P-Flash Freescale Semiconductor ...
Page 119
... BDM has priority over CPU12 when its access is stalled for more than 128 cycles. In the later case the CPU will be stalled after finishing the current operation and the BDM will gain access to the bus. 3.5.2 Interrupts The MMC does not generate any interrupts. Freescale Semiconductor CPU S12X0 MMC “Crossbar Switch” XBUS0 BDM ...
Page 120
... This sequence is uninterruptable. The RTC can be executed from anywhere in the local CPU memory space. The CALL and RTC instructions behave like JSR and RTS instruction, they however require more execution cycles. Usage of JSR/RTS instructions is therefore recommended when possible and 120 S12P-Family Reference Manual, Rev. 1.13 Freescale Semiconductor ...
Page 121
... RTC instruction must be called using the CALL instruction even when the correct page is already present in the memory map. This is to make sure that the correct PPAGE value will be present on stack at the time of the RTC instruction execution. Freescale Semiconductor S12P-Family Reference Manual, Rev. 1.13 Memory Map Control (S12PMMCV1) ...
Page 122
... Memory Map Control (S12PMMCV1) 122 S12P-Family Reference Manual, Rev. 1.13 Freescale Semiconductor ...
Page 123
... Features • Interrupt vector base register (IVBR) • One spurious interrupt vector (at address vector base Freescale Semiconductor Author updates for S12P family devices: - re-added XIRQ and IRQ references since this functionality is used on devices without D2D - added low voltage reset as possible source to the pin reset vector added clarifi ...
Page 124
... The vector base is a 16-bit address which is accumulated from the contents of the interrupt vector base register (IVBR, used as upper byte) and 0x00 (used as lower byte). 124 for details. for details. S12P-Family Reference Manual, Rev. 1.13 Section 4.5.3, “Wake Up Section 4.5.3, “Wake Up for details. Freescale Semiconductor ...
Page 125
... Interrupt Vector Base Register (IVBR) Address: 0x0120 Reset 1 1 Figure 4-2. Interrupt Vector Base Register (IVBR) Read: Anytime Write: Anytime Freescale Semiconductor I bit Maskable Channels Figure 4-1. INT Block Diagram 5 4 IVB_ADDR[7: S12P-Family Reference Manual, Rev. 1.13 Interrupt Module (S12SINTV1) Wake Up CPU ...
Page 126
... In this case, the CPU will receive the highest priority vector and the system will process this interrupt request first, before the original interrupt request is processed. 126 Table 4-3. IVBR Field Descriptions Description NOTE S12P-Family Reference Manual, Rev. 1.13 Freescale Semiconductor ...
Page 127
... Spurious interrupt 1. 16 bits vector address based 2. D2D error interrupt on MCUs featuring a D2D initiator module, otherwise XIRQ pin interrupt 3. D2D interrupt on MCUs featuring a D2D initiator module, otherwise IRQ pin interrupt Freescale Semiconductor NOTE Table 4-4. Table 4-4. Exception Vector Map and Priority (3) S12P-Family Reference Manual, Rev ...
Page 128
... The capability of the XIRQ pin to wake-up the MCU with the X bit set may not be available if, for example, the XIRQ pin is shared with other peripheral modules on the device. Please refer to the Device section of the MCU reference manual for details. 128 S12P-Family Reference Manual, Rev. 1.13 Freescale Semiconductor ...
Page 129
... X interrupt request used for wake-up remains active at least until the system begins execution of the instruction following the WAI or STOP instruction; otherwise, wake-up may not occur. Freescale Semiconductor S12P-Family Reference Manual, Rev. 1.13 Interrupt Module (S12SINTV1) 129 ...
Page 130
... Interrupt Module (S12SINTV1) 130 S12P-Family Reference Manual, Rev. 1.13 Freescale Semiconductor ...
Page 131
... Family ID readable from BDM ROM at global address 0x3_FF0F in active BDM (value for devices with HCS12S core is 0xC2) • Clock switch removed from BDM (CLKSW bit removed from BDMSTS register) Freescale Semiconductor General First version of S12SBDMV1 General Updated register address information & Block Version 5 ...
Page 132
... If the device is in secure mode, the operation of the BDM is reduced to a small subset of its regular run mode operation. Secure operation prevents access to Flash other than allowing erasure. For more information please see Section 5.4.1, 132 “Security”. S12P-Family Reference Manual, Rev. 1.13 Freescale Semiconductor ...
Page 133
... The communication rate of this pin is based on the settings for the VCO clock (CPMUSYNR). The BDM clock frequency is always VCO clock frequency divided by 8. After reset the BDM clock is based on the reset values of the CPMUSYNR register (4 MHz). When modifying the VCO Freescale Semiconductor Figure 5-1. ...
Page 134
... Family ID (part of BDM firmware ROM) BDM firmware ROM BDMACT 0 SDV Unimplemented, Reserved = Indeterminate Figure 5-2. BDM Register Summary S12P-Family Reference Manual, Rev. 1.13 Size (Bytes 240 Figure 5-2. Registers are accessed TRACE 0 UNSEC Implemented (do not alter) = Always read zero 0 Freescale Semiconductor Bit ...
Page 135
... This is because the ENBDM bit is set by the standard BDM firmware before a BDM command can be fully transmitted and executed. 2. UNSEC is read debugging environment in special single chip mode when the device is secured and fully erased, else and can only be read if not secure (see also bit description). Freescale Semiconductor ...
Page 136
... Flash EEPROM is configured for unsecure mode. 136 Table 5-2. BDMSTS Field Descriptions Description S12P-Family Reference Manual, Rev. 1.13 Freescale Semiconductor ...
Page 137
... BDM Program Paging disabled 1 BDM Program Paging enabled 3–0 BDM Program Page Index Bits 3–0 — These bits define the selected program page. For more detailed BPP[3:0] information regarding the program page window scheme, please refer to the S12S_MMC Block Guide. Freescale Semiconductor CCR6 CCR5 ...
Page 138
... Hardware BACKGROUND command 1. BDM is enabled and active immediately out of special single-chip reset. 138 Commands”. Target system memory Commands”. The CPU resources referred to are the Commands”) and in secure mode (see 1 : S12P-Family Reference Manual, Rev. 1.13 Section 5.4.1, does Freescale Semiconductor ...
Page 139
... The READ_BD and WRITE_BD commands allow access to the BDM register locations. These locations are not normally in the system memory map but share addresses with the application in memory. To distinguish between physical memory locations that share the same address, BDM memory resources are 1. This method is provided by the S12S_DBG module. Freescale Semiconductor 1 NOTE Table 5-4 ...
Page 140
... Write to memory with standard BDM firmware lookup table out of map. Odd address data on low byte; even address data on high byte. Write to memory with standard BDM firmware lookup table out of map. Must be aligned access. Section 5.4.2, “Enabling and Activating Table 5-5. S12P-Family Reference Manual, Rev. 1.13 Description BDM”. Freescale Semiconductor ...
Page 141
... If attempted by BDM hardware command, the BDM ignores the least significant bit of the address and assumes an even address from the remaining bits. Freescale Semiconductor Table 5-5. Firmware Commands Data Increment X index register 2), then write word to location pointed ...
Page 142
... Target clock cycles are cycles measured using the target MCU’s serial clock rate. See and Section 5.3.2.1, “BDM Status Register (BDMSTS)” 142 NOTE for information on how serial clock rate is selected. S12P-Family Reference Manual, Rev. 1.13 1 Section 5.4.6, “BDM Serial Interface” Freescale Semiconductor ...
Page 143
... The target measures delays from this perceived start of the bit time while the host measures delays from the point it actually drove BKGD low to start the bit up to one target clock cycle Freescale Semiconductor 16 Bits 150-BC ...
Page 144
... The host should sample the bit level about 10 target clock cycles after it started the bit time. 144 Target Senses Bit 10 Cycles Figure 5-8 shows the host receiving a logic 1 from the target S12P-Family Reference Manual, Rev. 1.13 Earliest Start of Next Bit Freescale Semiconductor ...
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... MCU) Host Drive to BKGD Pin Target System Drive and Speedup Pulse Perceived Start of Bit Time BKGD Pin Figure 5-9. BDM Target-to-Host Serial Bit Timing (Logic 0) Freescale Semiconductor High-Impedance R-C Rise 10 Cycles 10 Cycles Host Samples BKGD Pin High-Impedance 10 Cycles 10 Cycles Host Samples BKGD Pin S12P-Family Reference Manual, Rev ...
Page 146
... Figure 5-10). This pulse is referred to as the ACK pulse. 16 Cycles Minimum Delay From the BDM Command Figure 5-10. Target Acknowledge Pulse (ACK) NOTE S12P-Family Reference Manual, Rev. 1.13 (CPMUSYNR very 8. The alternative High-Impedance Speedup Pulse Earliest Start of Next Bit Freescale Semiconductor ...
Page 147
... After a certain time the host (not aware of stop or wait) should decide to abort any possible pending ACK pulse in order to be sure a new command can be issued. Therefore, the protocol provides a mechanism in which a command, and its corresponding ACK, can be aborted. Freescale Semiconductor BDM Executes the BDM Decodes ...
Page 148
... The details about the short abort pulse are being provided only as a reference for the reader to better understand the BDM internal behavior not recommended that this procedure be used in a real application. 148 NOTE Pulse”, and assumes that the pending command NOTE S12P-Family Reference Manual, Rev. 1.13 Procedure”. Freescale Semiconductor ...
Page 149
... MCU) Target MCU Drives to BKGD Pin Host Drives SYNC To BKGD Pin BKGD Pin Figure 5-13. ACK Pulse and SYNC Request Conflict Freescale Semiconductor SYNC Response From the Target (Out of Scale) (Out of Scale) READ_STATUS Host BDM Decode NOTE At Least 128 Cycles ...
Page 150
... The TRACE1 command has the related ACK pulse issued when the CPU enters background active mode after one instruction of the application program is executed. The ACK pulse related to this command could be aborted using the SYNC command. 150 NOTE and Section 5.4.4, “Standard BDM Firmware Commands” S12P-Family Reference Manual, Rev. 1.13 Freescale Semiconductor ...
Page 151
... BDM firmware and the BDM is active and ready to receive a new command. If the TRACE1 command is issued again, the next user instruction will be executed. This facilitates stepping or tracing through the user code one instruction at a time. Freescale Semiconductor S12P-Family Reference Manual, Rev. 1.13 Background Debug Module (S12SBDMV1) ...
Page 152
... The data is not available for retrieval after the time-out has occurred. This is the expected behavior if the handshake protocol is not enabled. In order to allow the data to be retrieved even with a large clock frequency mismatch (between BDM and CPU) when the hardware 152 S12P-Family Reference Manual, Rev. 1.13 Freescale Semiconductor ...
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... The next negative edge in the BKGD pin, after a soft-reset has occurred, is considered by the target as the start of a new BDM command, or the start of a SYNC request pulse. Freescale Semiconductor S12P-Family Reference Manual, Rev. 1.13 Background Debug Module (S12SBDMV1) ...
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... Background Debug Module (S12SBDMV1) 154 S12P-Family Reference Manual, Rev. 1.13 Freescale Semiconductor ...
Page 155
... CPU: S12SCPU module DBG: S12SDBG module POR: Power On Reset Tag: Tags can be attached to CPU opcodes as they enter the instruction pipe. If the tagged opcode reaches the execution stage a tag hit occurs. Freescale Semiconductor Table 6-1. Revision History Sections Affected 6.5 Added application information General Spelling corrections ...
Page 156
... Compressed Pure PC: all program counter addresses are stored • 4-stage state sequencer for trace buffer control — Tracing session trigger linked to Final State of state sequencer — Begin and End alignment of tracing to trigger 156 S12P-Family Reference Manual, Rev. 1.13 Freescale Semiconductor ...
Page 157
... COMPARATOR A CPU BUS COMPARATOR B COMPARATOR C READ TRACE DATA (DBG READ DATA BUS) 6.2 External Signal Description There are no external signals associated with this module. Freescale Semiconductor Comparator Breakpoints Matches Enabled Possible Yes Yes Only SWI Active BDM not possible when not enabled ...
Page 158
... SSF1 0 TRCMOD 0 0 ABCM Bit 11 Bit 10 Bit 9 Bit 3 Bit 2 Bit 1 CNT SC3 SC2 SC1 0 MC2 MC1 RW RWE NDB 0 RW RWE 0 RW RWE 0 0 Bit Freescale Semiconductor Bit 0 SSF0 TALIGN Bit 8 Bit 0 SC0 MC0 COMPE COMPE COMPE Bit 16 Bit 8 Bit 0 Bit 8 Bit 0 ...
Page 159
... Bits 4:3 anytime DBG is not armed. When disarming the DBG by clearing ARM with software, the contents of bits[4:3] are not affected by the write, since up until the write operation, ARM = 1 preventing these bits from being written. These bits must be cleared using a second write if required. Freescale Semiconductor ...
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... Table 6-3. DBGC1 Field Descriptions Description Table 6-4. COMRV Encoding Visible Comparator Visible Register at 0x0027 Comparator A Comparator B Comparator C None Figure 6-4. Debug Status Register (DBGSR) S12P-Family Reference Manual, Rev. 1.13 Table 6-4. DBGSCR1 DBGSCR2 DBGSCR3 DBGMFR SSF2 SSF1 Freescale Semiconductor 0 SSF0 0 0 ...
Page 161
... Trace Source Control Bit — The TSOURCE bit enables a tracing session given a trigger condition. If the MCU TSOURCE system is secured, this bit cannot be set and tracing is inhibited. This bit must be set to read the trace buffer. 0 Debug session without tracing requested 1 Debug session with tracing requested Freescale Semiconductor Table 6-5. DBGSR Field Descriptions Description SSF[2:0] Current State 000 ...
Page 162
... Table 6-8. TRCMOD Trace Mode Bit Encoding Description Normal Loop1 Detail Compressed Pure Figure 6-6. Debug Control Register2 (DBGC2) Table 6-9. DBGC2 Field Descriptions Description Table 6-10. ABCM Encoding Description Match 0 mapped to comparator A/B inside range: Match1 disabled. S12P-Family Reference Manual, Rev. 1. ABCM Freescale Semiconductor Table 6- ...
Page 163
... The POR state is undefined. Other resets do not affect the trace buffer contents. 6.3.2.6 Debug Count Register (DBGCNT) Address: 0x0026 TBF 0 W Reset — — POR Unimplemented or Reserved Read: Anytime Write: Never Freescale Semiconductor Table 6-10. ABCM Encoding Description Reserved Bit 8 Bit — — — ...
Page 164
... ARM bit will be cleared and the tracing session ends. .. oldest data has been overwritten by most recent data .. COMRV Visible State Control Register 00 DBGSCR1 01 DBGSCR2 10 DBGSCR3 11 DBGMFR S12P-Family Reference Manual, Rev. 1.13 Description No data valid 1 line valid 2 lines valid 4 lines valid 6 lines valid .. 63 lines valid 64 lines valid, Freescale Semiconductor ...
Page 165
... The priorities described in Table 6-36 final state has priority followed by the match on the lower channel number (0,1,2). Thus with SC[3:0]=1101 a simultaneous match0/match1 transitions to final state. Freescale Semiconductor SC3 and described in 6.3.2.8.1. Comparators must be enabled by setting Table 6-15 ...
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... Either Match0 or Match1 to Final State Reserved Reserved Reserved Reserved Either Match0 or Match1 to Final State........Match2 to State3 Reserved Reserved Either Match0 or Match1 to Final State........Match2 to State1 dictate that in the case of simultaneous matches, a match leading to S12P-Family Reference Manual, Rev. 1. SC2 SC1 0 0 Freescale Semiconductor 0 SC0 0 ...
Page 167
... The priorities described in Table 6-36 final state has priority followed by the match on the lower channel number (0,1,2). Freescale Semiconductor SC3 and described in 6.3.2.8.1. Comparators must be enabled by setting Table 6-19. DBGSCR3 Field Descriptions Description Description (Unspecifi ...
Page 168
... Table 6-21. Comparator Register Layout Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write S12P-Family Reference Manual, Rev. 1. MC2 MC1 MC0 Comparators A,B and C Comparators A,B and C Comparators A,B and C Comparators A,B and C Comparator A only Comparator A only Comparator A only Comparator A only Freescale Semiconductor ...
Page 169
... Size Comparator Value Bit — The SZ bit selects either word or byte access size in comparison for the SZ associated comparator. This bit is ignored if the SZE bit is cleared or if the TAG bit in the same register is set. (Comparators 0 Word access size is compared A and B) 1 Byte access size is compared Freescale Semiconductor TAG BRK RW ...
Page 170
... TAG bit is set since the match occurs based on the tagged opcode reaching the execution stage of the instruction queue. Table 6-23. Read or Write Comparison Logic Table RWE Bit 170 Description RW Bit RW Signal S12P-Family Reference Manual, Rev. 1.13 Comment RW not used in comparison RW not used in comparison Write data bus No match No match Read data bus Freescale Semiconductor ...
Page 171
... Debug Comparator Address Mid Register (DBGXAM) Address: 0x002A Bit 15 Bit 14 W Reset 0 0 Figure 6-17. Debug Comparator Address Mid Register (DBGXAM) Read: Anytime. See Table 6-24 Write: If DBG not armed. See Freescale Semiconductor Table 6-24. COMRV Visible Comparator 00 DBGAAH, DBGAAM, DBGAAL 01 DBGBAH, DBGBAM, DBGBAL 10 ...
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... Table 6-26. DBGXAM Field Descriptions Description 5 4 Bit 5 Bit for visible register encoding. Table 6-24 for visible register encoding. Table 6-27. DBGXAL Field Descriptions Description 5 4 Bit 13 Bit 12 Bit S12P-Family Reference Manual, Rev. 1. Bit 3 Bit 2 Bit Bit 10 Bit Freescale Semiconductor 0 Bit Bit 8 0 ...
Page 173
... Address: 0x002E Bit 15 Bit 14 W Reset 0 0 Figure 6-21. Debug Comparator Data High Mask Register (DBGADHM) Read: If COMRV[1: Write: If COMRV[1: and DBG not armed. Freescale Semiconductor Table 6-28. DBGADH Field Descriptions Description Bit 5 Bit 4 Bit Table 6-29. DBGADL Field Descriptions Description ...
Page 174
... A match with a comparator register value can initiate a state sequencer transition to another state (see 174 Table 6-30. DBGADHM Field Descriptions Description 5 4 Bit 5 Bit 4 Bit Table 6-31. DBGADLM Field Descriptions Description Figure 6-24). Either forced or tagged matches are possible. Using S12P-Family Reference Manual, Rev. 1. Bit 2 Bit Freescale Semiconductor 0 Bit 0 0 ...
Page 175
... RWE, RW, SZE, and SZ bits. The RWE bit controls whether read or write comparison is enabled for the associated comparator and the RW bit selects either a read or write access for a valid match. Similarly the SZE and Freescale Semiconductor MATCH0 MATCH ...
Page 176
... SZ bit value such that only the specified size of 176 Comp C Address RWE (1) ADDR[n] ADDR[n] ADDR[n] S12P-Family Reference Manual, Rev. 1.13 RW Examples 0 X LDAA ADDR[n] STAA #$BYTE ADDR[ STAA #$BYTE ADDR[ LDAA #$BYTE ADDR[n] Freescale Semiconductor ...
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... Word, data(ADDR[n])=X, data(ADDR[n+1])= $FF00 Word, data(ADDR[n])=DH, data(ADDR[n+1])= $FFFF Word, data(ADDR[n])=DH, data(ADDR[n+1])= $0000 Byte 1 1 $FF00 Byte, data(ADDR[n])=DH Freescale Semiconductor Comp B Address RWE SZE (1) ADDR[n] 0 ADDR[n] 0 ADDR[n] 0 Access DH=DBGADH, DL=DBGADL S12P-Family Reference Manual, Rev. 1.13 S12S Debug Module (S12SDBGV2) SZ8 Examples 0 X ...
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... Table 6-35. NDB and MASK bit dependency Do not compare data bus bit. Compare data bus bit. Match on equivalence. Do not compare data bus bit. Compare data bus bit. Match on difference. S12P-Family Reference Manual, Rev. 1.13 Comment Freescale Semiconductor ...
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... It is thus possible to miss a lower priority match if it occurs simultaneously with a higher priority. The priorities described in pointing to final state has highest priority followed by the lower channel number (0,1,2). Freescale Semiconductor Table 6-36 dictate that in the case of simultaneous matches, the match S12P-Family Reference Manual, Rev. 1.13 ...
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... Transition to next state as defined by state control registers Transition to next state as defined by state control registers Transition to next state as defined by state control registers ARM = 1 State1 ARM = 0 (Disarm) Final State Figure 6-24. State Sequencer Diagram S12P-Family Reference Manual, Rev. 1.13 Action Enter Final State State2 State3 Freescale Semiconductor ...
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... Trace Modes Four trace modes are available. The mode is selected using the TRCMOD bits in the DBGTCR register. Tracing is enabled using the TSOURCE bit in the DBGTCR register. The modes are described in the following subsections. Freescale Semiconductor Table 6-37 and Table 6-40. After each store the counter register S12P-Family Reference Manual, Rev ...
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... ADDR1 DBNE A,PART5 182 NOTE ; IRQ interrupt occurs during execution of this ; ; JMP Destination address TRACE BUFFER ENTRY 1 ; RTI Destination address TRACE BUFFER ENTRY Source address TRACE BUFFER ENTRY 4 ; IRQ Vector $FFF2 = TRACE BUFFER ENTRY S12P-Family Reference Manual, Rev. 1.13 Freescale Semiconductor ...
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... In this case DBGCNT bits are incremented twice, once for the address line and once for the data line, on Freescale Semiconductor NOTE: S12P-Family Reference Manual, Rev. 1.13 ...
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... DATAH1 ADRM2 0 DATAH2 PCH1 PCM1 PCH2 PCM2 Bit 3 Bit 2 Bit 1 CSZ CRW ADDR[17] ADDR[16] Figure 6-25. Field2 Bits in Detail Mode Table 6-38. Field Descriptions Description S12P-Family Reference Manual, Rev. 1.13 8-bits Field 0 ADRL1 DATAL1 ADRL2 DATAL2 PCL1 PCL2 Bit 0 Freescale Semiconductor ...
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... Line 1, PC1, is overwritten with a new entry. Thus the entries on Lines 2 and 3 have lost their base address. For reconstruction of program flow the first base address following the pointer must be used, in the example, Line 4. The pointer points to the oldest entry, Line 2. Freescale Semiconductor Bit 3 Bit 2 Bit 1 ...
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... DBGCNT. The internal pointer to the current 186 TRACE BUFFER ROW CONTENT S12P-Family Reference Manual, Rev. 1.13 Table 6-37. The Freescale Semiconductor ...
Page 187
... Breakpoints can be generated when the state sequencer transitions to the Final State. If configured for tagging, then the breakpoint is generated when the tagged opcode reaches the execution stage of the instruction queue. Freescale Semiconductor NOTE S12P-Family Reference Manual, Rev. 1.13 S12S Debug Module (S12SDBGV2) ...
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... Start Trace Buffer at trigger (no breakpoints breakpoint request occurs when Trace Buffer is full 1 Terminate tracing and generate breakpoint immediately on trigger 0 Terminate tracing immediately on trigger Table 6-42 tracing session is selected, breakpoints are S12P-Family Reference Manual, Rev. 1.13 Breakpoint Alignment Start Trace Buffer at trigger Freescale Semiconductor ...
Page 189
... SCR encoding supported by S12SDBGV1 are shown in black. SCR encoding supported only in S12SDBGV2 are shown in red. For backwards compatibility the new scenarios use a 4th bit in each SCR register. Thus the existing encoding for SCRx[2:0] is not changed. Freescale Semiconductor Table 6-43. Breakpoint Mapping Summary BDM ...
Page 190
... All 3 scenarios 2a,2b,2c are possible with the S12SDBGV1 SCR encoding 190 Figure 6-27. Scenario 1 SCR2=0010 SCR3=0111 M2 State3 State2 Figure 6-28. Scenario 2a SCR2=0101 M2 Final State State2 Figure 6-29. Scenario 2b SCR2=0101 M2 Final State State2 Figure 6-30. Scenario 2c SCR2=0011 M0 Final State State2 S12P-Family Reference Manual, Rev. 1.13 M0 Final State Freescale Semiconductor ...
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... This scenario is currently not possible using 2 comparators only. S12SDBGV2 makes it possible with 2 comparators, State 3 allowing return to state 2, whilst a M2 leads to final state as shown. Figure 6-33. Scenario 4b (with 2 comparators) SCR1=0110 SCR3=1110 The advantage of using only 2 channels is that now range comparisons can be included (channel0) Freescale Semiconductor Figure 6-31. Scenario 3 SCR1=0000 M012 Final State State1 Figure 6-32 ...
Page 192
... Trigger when a series of 3 events is executed out of order. Specifying the event order as M1,M2,M0 to run in loops (120120120). Any deviation from that order should trigger. This scenario is not possible using the 192 Figure 6-34. Scenario 5 SCR2=0110 M0 M1 State2 M2 Figure 6-35. Scenario 6 SCR3=1010 M0 M0 State3 M12 S12P-Family Reference Manual, Rev. 1.13 Final State Final State Freescale Semiconductor ...
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... Trigger when a routine/event at M2 follows either M1 or M0. SCR1=0111 M01 State1 Trigger when an event M2 is followed by either event M0 or event M1 SCR1=0010 M2 State1 Scenario 8a and 8b are possible with the S12SDBGV1 and S12SDBGV2 SCR encoding Freescale Semiconductor Figure 6-36. Scenario 7 SCR2=1100 SCR3=1101 M2 State3 State2 M0 M02 Figure 6-37 ...
Page 194
... M2 must always be followed by M1 before M0. If after any M2, event M0 occurs before M1 then a trigger is generated. 194 Figure 6-39. Scenario 9 SCR2=1111 M01 M01 State2 M2 Figure 6-40. Scenario 10a SCR2=0100 SCR3=0010 M2 State3 State2 M1 Figure 6-41. Scenario 10b SCR2=0011 SCR3=0000 M1 State3 State2 M0 S12P-Family Reference Manual, Rev. 1.13 Final State M0 Final State M0 Final State Freescale Semiconductor ...
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... Freescale Semiconductor S12P-Family Reference Manual, Rev. 1.13 S12S Debug Module (S12SDBGV2) 195 ...
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... S12S Debug Module (S12SDBGV2) 196 S12P-Family Reference Manual, Rev. 1.13 Freescale Semiconductor ...
Page 197
... The Pierce Oscillator (OSCLCP) contains circuitry to dynamically control current gain in the output amplitude. This ensures a signal with low harmonic distortion, low power and good noise immunity. • Supports crystals or resonators from 4MHz to 16MHz. Freescale Semiconductor Author Initial release added IRCLK to Block Diagram clarifi ...
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... System Reset generation from the following possible sources: — Power-on reset (POR) — Low-voltage reset (LVR) — Illegal address access — COP time out — Loss of oscillation (clock monitor fail) — External pin RESET 198 S12P-Family Reference Manual, Rev. 1.13 Freescale Semiconductor ...
Page 199
... Select the Oscillator Clock (OSCCLK) as Bus Clock (PLLSEL=0). — The PLLCLK is still on to filter possible spikes of the external oscillator clock. 7.1.2.2 Wait Mode For S12CPMU Wait Mode is the same as Run Mode. Freescale Semiconductor S12 Clock, Reset and Power Management Unit (S12CPMU) S12P-Family Reference Manual, Rev. 1.13 199 ...
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... When starting up the external oscillator (either by programming OSCE bit exit from Full Stop Mode with OSCE bit already 1) the software must wait for a minimum time equivalent to the startup-time of the external oscillator t UPOSC 200 NOTE before entering Pseudo Stop Mode. S12P-Family Reference Manual, Rev. 1.13 Freescale Semiconductor ...