MC908QY8CPE Freescale Semiconductor, MC908QY8CPE Datasheet - Page 122

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MC908QY8CPE

Manufacturer Part Number
MC908QY8CPE
Description
IC MCU 8BIT 8K FLASH 16-DIP
Manufacturer
Freescale Semiconductor
Series
HC08r
Datasheet

Specifications of MC908QY8CPE

Core Processor
HC08
Core Size
8-Bit
Speed
8MHz
Peripherals
LVD, POR, PWM
Number Of I /o
13
Program Memory Size
8KB (8K x 8)
Program Memory Type
FLASH
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 4x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
16-DIP (0.300", 7.62mm)
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Connectivity
-

Available stocks

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Part Number
Manufacturer
Quantity
Price
Part Number:
MC908QY8CPE
Manufacturer:
FREESCALE
Quantity:
20 000
Enhanced Serial Communications Interface (ESCI) Module
13.8.1 ESCI Control Register 1
ESCI control register 1 (SCC1):
LOOPS — Loop Mode Select Bit
ENSCI — Enable ESCI Bit
TXINV — Transmit Inversion Bit
M — Mode (Character Length) Bit
122
This read/write bit enables loop mode operation. In loop mode the RxD pin is disconnected from the
ESCI, and the transmitter output goes into the receiver input. Both the transmitter and the receiver
must be enabled to use loop mode.
This read/write bit enables the ESCI and the ESCI baud rate generator. Clearing ENSCI sets the SCTE
and TC bits in ESCI status register 1 and disables transmitter interrupts.
This read/write bit reverses the polarity of transmitted data.
This read/write bit determines whether ESCI characters are eight or nine bits long (see
Table
1 = Loop mode enabled
0 = Normal operation enabled
1 = ESCI enabled
0 = ESCI disabled
1 = Transmitter output inverted
0 = Transmitter output not inverted
1 = 9-bit ESCI characters
0 = 8-bit ESCI characters
Enables loop mode operation
Enables the ESCI
Controls output polarity
Controls character length
Controls ESCI wakeup method
Controls idle character detection
Enables parity function
Controls parity type
13-4).The ninth bit can serve as a receiver wakeup signal or as a parity bit.
Reset:
Read:
Write:
Setting the TXINV bit inverts all transmitted values including idle, break,
start, and stop bits.
LOOPS
Bit 7
0
Figure 13-9. ESCI Control Register 1 (SCC1)
ENSCI
6
0
MC68HC908QB8 Data Sheet, Rev. 3
TXINV
5
0
NOTE
M
0
4
WAKE
3
0
ILTY
2
0
PEN
1
0
Freescale Semiconductor
Bit 0
PTY
0

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