MC9S08DV32ACLC Freescale Semiconductor, MC9S08DV32ACLC Datasheet - Page 259

• Manufacturer Part Number: MC9S08DV32ACLC
• Description: IC MCU 32K FLASH 2K RAM 32-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS08r

Specifications of MC9S08DV32ACLC

• Core Processor: HCS08
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: CAN, I²C, LIN, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 25
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 10x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-LQFP
• Controller Family/series: HCS08
• No. Of I/o's: 25
• Ram Memory Size: 2KB
• Cpu Speed: 40MHz
• No. Of Timers: 2
• Digital Ic Case Style: LQFP
• Rohs Compliant: Yes
• Processor Series: S08DV
• Core: HCS08
• Data Bus Width: 8 bit
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWS08
• Development Tools By Supplier: DEMO9S08DZ60
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

The synchronization jump width (see the Bosch CAN specification for details) can be programmed in a
range of 1 to 4 time quanta by setting the SJW parameter.
The SYNC_SEG, TSEG1, TSEG2, and SJW parameters are set by programming the MSCAN bus timing
registers (CANBTR0, CANBTR1) (see
and
Table 12-35
12.5.4
12.5.4.1
The MSCAN module behaves as described within this specification in all normal system operation modes.
12.5.4.2
The MSCAN module behaves as described within this specification in all special system operation modes.
Freescale Semiconductor
Section 12.3.4, “MSCAN Bus Timing Register 1
Time Segment 1
Modes of Operation
gives an overview of the CAN compliant segment settings and the related parameter values.
Normal Modes
Special Modes
5 .. 10
4 .. 11
5 .. 12
6 .. 13
7 .. 14
8 .. 15
9 .. 16
It is the user’s responsibility to ensure the bit time settings are in compliance
with the CAN standard.
Transmit Point
Sample Point
SYNC_SEG
Syntax
Table 12-35. CAN Standard Compliant Bit Time Segment Settings
TSEG1
3 .. 10
4 .. 11
5 .. 12
6 .. 13
7 .. 14
8 .. 15
4 .. 9
System expects transitions to occur on the CAN bus during this
period.
A node in transmit mode transfers a new value to the CAN bus at
this point.
A node in receive mode samples the CAN bus at this point. If the
three samples per bit option is selected, then this point marks the
position of the third sample.
MC9S08DV60 Series Data Sheet, Rev 3
Table 12-34. Time Segment Syntax
Time Segment 2
Section 12.3.3, “MSCAN Bus Timing Register 0
2
3
4
5
6
7
8
NOTE
(CANBTR1)”).
Chapter 12 Freescale’s Controller Area Network (S08MSCANV1)
Description
TSEG2
1
2
3
4
5
6
7
Synchronization
Jump Width
1 .. 2
1 .. 3
1 .. 4
1 .. 4
1 .. 4
1 .. 4
1 .. 4
(CANBTR0)”
SJW
0 .. 1
0 .. 2
0 .. 3
0 .. 3
0 .. 3
0 .. 3
0 .. 3
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