MC908JL16CDWE Freescale Semiconductor, MC908JL16CDWE Datasheet - Page 141

• Manufacturer Part Number: MC908JL16CDWE
• Description: IC MCU 16K FLASH 8MHZ 28-SOIC
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC908JL16CDWE

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: I²C, SCI
• Peripherals: LED, LVD, POR, PWM
• Number Of I /o: 23
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-SOIC (7.5mm Width)
• Controller Family/series: HC08
• No. Of I/o's: 23
• Ram Memory Size: 512Byte
• Cpu Speed: 8MHz
• No. Of Timers: 2
• Embedded Interface Type: I2C, SCI
• Rohs Compliant: Yes
• Processor Series: HC08JL
• Core: HC08
• Data Bus Width: 8 bit
• Data Ram Size: 512 B
• Interface Type: SCI
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 23
• Number Of Timers: 4
• Operating Supply Voltage: 2.7 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: FSICEBASE, DEMO908JL16E, M68CBL05CE
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 12 Channel
• For Use With: DEMO908JL16E - BOARD DEMO FOR MC908JL16
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

10.2.2 Data Direction Register A (DDRA)
Data direction register A determines whether each port A pin is an input or an output. Writing a logic 1 to
a DDRA bit enables the output buffer for the corresponding port A pin; a logic 0 disables the output buffer.
DDRA[7:0] — Data Direction Register A Bits
Figure 10-4
When DDRAx is a logic 1, reading address $0000 reads the PTAx data latch. When DDRAx is a logic 0,
reading address $0000 reads the voltage level on the pin. The data latch can always be written,
regardless of the state of its data direction bit.
Freescale Semiconductor
These read/write bits control port A data direction. Reset clears DDRA[7:0], configuring all port A pins
as inputs.
1 = Corresponding port A pin configured as output
0 = Corresponding port A pin configured as input
shows the port A I/O logic.
Address: $0004
For those devices packaged in a 28-pin package, PTA7 is not connected.
DDRA7 should be set to a 1 to configure PTA7 as an output.
Avoid glitches on port A pins by writing to the port A data register before
changing data direction register A bits from 0 to 1.
Reset:
Read:
Write:
READ DDRA ($0004)
WRITE DDRA ($0004)
WRITE PTA ($0000)
READ PTA ($0000)
DDRA7
Bit 7
0
Figure 10-3. Data Direction Register A (DDRA)
DDRA6
6
0
RESET
MC68HC908JL16 Data Sheet, Rev. 1.1
Figure 10-4. Port A I/O Circuit
DDRA5
5
0
NOTE
NOTE
DDRA4
DDRAx
PTAx
4
0
DDRA3
3
0
DDRA2
2
0
PTAPUEx
DDRA1
1
0
To KBI
DDRA0
Bit 0
PTAx
0
Port A
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