MCF51AC128AVFUE Freescale Semiconductor, MCF51AC128AVFUE Datasheet - Page 6

• Manufacturer Part Number: MCF51AC128AVFUE
• Description: MCU 32BIT 128K FLASH CAN 64-QFP
• Manufacturer: Freescale Semiconductor
• Series: MCF51ACr

Specifications of MCF51AC128AVFUE

• Core Processor: Coldfire V1
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: CAN, I²C, SCI, SPI
• Peripherals: LVD, PWM, WDT
• Number Of I /o: 54
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 20x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 64-QFP
• Processor Series: MCF51AC
• Core: ColdFire V1
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: SCI, SPI
• Maximum Clock Frequency: 50.33 MHz
• Number Of Programmable I/os: 54
• Number Of Timers: 8
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 20 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

MCF51AC256 Family Configurations
1.3.1
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32-bit Version 1 ColdFire® central processor unit (CPU)
— Up to 50.33 MHz at 2.7 V – 5.5 V
— Provide 0.94 Dhrystone 2.1 DMIPS per MHz performance when running from internal RAM
— Implements instruction set revision C (ISA_C)
On-chip memory
— Up to 256 KB flash memory read/program/erase over full operating voltage and temperature
— Up to 32 KB static random access memory (SRAM)
— Security circuitry to prevent unauthorized access to SRAM and flash contents
Power-Saving Modes
— Three low-power stop plus wait modes
— Peripheral clock enable register can disable clocks to unused modules, reducing currents;
System protection features
— Watchdog computer operating properly (COP) reset with options to run from independent LPO
— Low-voltage detection with reset or interrupt
— Illegal opcode and illegal address detection with programmable reset or exception response
— Flash block protection
Debug support
— Single-wire background debug interface
— Real-time debug support, with 6 hardware breakpoints (4 PC, 1 address pair and 1 data) that
— On-chip trace buffer provides programmable start/stop recording conditions plus support for
— Support for real-time program (and optional partial data) trace using the debug visibility bus
V1 ColdFire interrupt controller (CF1_INTC)
— Support of 40 peripheral I/O interrupt requests plus seven software (one per level) interrupt
— Fixed association between interrupt request source and level plus priority, up to two requests
— Unique vector number for each interrupt source
— Support for service routine interrupt acknowledge (software IACK) read cycles for improved
Multipurpose clock generator (MCG)
— Oscillator (XOSC); loop-control Pierce oscillator; crystal or ceramic resonator range of 31.25
— LPO clock as an optional independent clock source for COP and RTI
— FLL/PLL controlled by internal or external reference
(0.76 DMIPS per MHz when running from flash)
allows clocks to remain enabled to specific peripherals in stop3 mode
clock or bus clock
can be configured into a 1- or 2-level trigger
continuous or PC-profiling modes
requests
can be remapped to the highest maskable level + priority
system performance
kHz to 38.4 kHz or 1 MHz to 16 MHz
Feature List
MCF51AC256 ColdFire Microcontroller Data Sheet, Rev.6
Freescale Semiconductor