MC908LJ12CFBE Freescale Semiconductor, MC908LJ12CFBE Datasheet - Page 287

• Manufacturer Part Number: MC908LJ12CFBE
• Description: IC MCU 12K FLASH 8MHZ 52-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC908LJ12CFBE

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: IRSCI, SPI
• Peripherals: LCD, LVD, POR, PWM
• Number Of I /o: 20
• Program Memory Size: 12KB (12K x 8)
• Program Memory Type: FLASH
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 52-LQFP
• Processor Series: HC08LJ
• Core: HC08
• Data Bus Width: 8 bit
• Data Ram Size: 512 B
• Interface Type: SCI/SPI
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 4
• Operating Supply Voltage: 3.3 V, 5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: FSICEBASE, M68EML08LJLKE, ZK-HC08LX-A, M68CBL05CE
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 6-ch x 10-bit
• Controller Family/series: HC08
• No. Of I/o's: 20
• Ram Memory Size: 512Byte
• Cpu Speed: 8MHz
• No. Of Timers: 2
• Embedded Interface Type: SCI, SPI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

MC68HC908LJ12
Freescale Semiconductor
—
Rev. 2.1
Reading the SPI status and control register with SPRF set and then
reading the receive data register clears SPRF. The clearing mechanism
for the SPTE flag is always just a write to the transmit data register.
The SPI transmitter interrupt enable bit (SPTIE) enables the SPTE flag
to generate transmitter CPU interrupt requests, provided that the SPI is
enabled (SPE = 1).
The SPI receiver interrupt enable bit (SPRIE) enables the SPRF bit to
generate receiver CPU interrupt requests, regardless of the state of the
SPE bit. (See
The error interrupt enable bit (ERRIE) enables both the MODF and
OVRF bits to generate a receiver/error CPU interrupt request.
The mode fault enable bit (MODFEN) can prevent the MODF flag from
being set so that only the OVRF bit is enabled by the ERRIE bit to
generate receiver/error CPU interrupt requests.
ERRIE
MODF
OVRF
R
Serial Peripheral Interface Module (SPI)
Figure 14-11. SPI Interrupt Request Generation
Figure
14-11.)
SPRIE
SPTE
SPTIE
SPRF
SPE
Serial Peripheral Interface Module (SPI)
NOT AVAILABLE
SPI TRANSMITTER
CPU INTERRUPT REQUEST
NOT AVAILABLE
SPI RECEIVER/ERROR
CPU INTERRUPT REQUEST
Technical Data
287