R5F21324ANSP#U1 Renesas Electronics America, R5F21324ANSP#U1 Datasheet - Page 184

• Manufacturer Part Number: R5F21324ANSP#U1
• Description: MCU 1KB FLASH 16K ROM 20-LSSOP
• Manufacturer: Renesas Electronics America
• Series: R8C/3x/32Ar

Specifications of R5F21324ANSP#U1

• Core Processor: R8C
• Core Size: 16/32-Bit
• Speed: 20MHz
• Connectivity: I²C, LIN, SIO, SSU, UART/USART
• Peripherals: POR, PWM, Voltage Detect, WDT
• Number Of I /o: 15
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 1.5K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 20-LSSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Under development
R8C/32A Group
REJ09B0458-0020 Rev.0.20
Page 154 of 583
13.2.2
Note:
When shipping
1. If the block including the OFS2 register is erased, the OFS2 register value is set to FFh.
Bits WDTRCS0 and WDTRCS1
(Watchdog Timer Refresh Acknowledgement Period Set Bit)
Bit
b0
b1
b2
b3
b4
b5
b6
b7
The OFS2 register is located on the flash memory. Write to this register with a program.
After writing, do not write additions to this register.
Assuming that the period from when the watchdog timer starts counting until it underflows is 100%, the refresh
acknowledgement period for the watchdog timer can be selected.
For details, refer to 14.3.1.1 Refresh Acknowledgment Period.
Address 0FFDBh
Symbol
WDTUFS0 Watchdog timer underflow period set bit
WDTUFS1
WDTRCS0 Watchdog timer refresh acknowledgement period
WDTRCS1
Symbol
Option Function Select Register 2 (OFS2)
Bit
—
—
—
—
Preliminary specification
Specifications in this manual are tentative and subject to change.
b7
—
1
set bit
Reserved bits
Nov 05, 2008
b6
—
1
b5
—
1
Bit Name
b4
—
1
WDTRCS1 WDTRCS0 WDTUFS1 WDTUFS0
b3
1
b1 b0
b3 b2
Set to 1.
0 0: 03FFh
0 1: 0FFFh
1 0: 1FFFh
1 1: 3FFFh
0 0: 25%
0 1: 50%
1 0: 75%
1 1: 100%
b2
1
13. Option Function Select Area
Function
b1
1
b0
1
(Note 1)
R/W
R/W
R/W
R/W
R/W
R/W