R5F21324ANSP#U1 Renesas Electronics America, R5F21324ANSP#U1 Datasheet - Page 283

• Manufacturer Part Number: R5F21324ANSP#U1
• Description: MCU 1KB FLASH 16K ROM 20-LSSOP
• Manufacturer: Renesas Electronics America
• Series: R8C/3x/32Ar

Specifications of R5F21324ANSP#U1

• Core Processor: R8C
• Core Size: 16/32-Bit
• Speed: 20MHz
• Connectivity: I²C, LIN, SIO, SSU, UART/USART
• Peripherals: POR, PWM, Voltage Detect, WDT
• Number Of I /o: 15
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 1.5K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 20-LSSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Under development
R8C/32A Group
REJ09B0458-0020 Rev.0.20
Page 253 of 583
19.5.4
Notes:
1. Enabled when in PWM mode.
2. Enabled when in output compare function, PWM mode, or PWM2 mode. For notes on PWM2 mode, refer to
3. Enabled when in PWM2 mode.
After Reset
Bit
b0
b1
b2
b3
b4
b5
b6
b7
Address 0130h
19.9.6 TRCMR Register in PWM2 Mode.
Symbol TCEG1
Symbol
TCEG0 TRCTRG input edge select bit
TCEG1
Bit
POLB
POLC
POLD
CSEL
Timer RC Control Register 2 (TRCCR2) for Output Compare Function
—
—
Preliminary specification
Specifications in this manual are tentative and subject to change.
b7
0
PWM mode output level control
bit B
PWM mode output level control
bit C
PWM mode output level control
bit D
Nothing is assigned. If necessary, set to 0. When read, the content is 1.
TRC count operation select bit
(1)
(1)
(1)
TCEG0
b6
0
Nov 05, 2008
Bit Name
CSEL
b5
0
b4
—
(3)
(2)
1
0: TRCIOB output level selected as “L” active
1: TRCIOB output level selected as “H” active
0: TRCIOC output level selected as “L” active
1: TRCIOC output level selected as “H” active
0: TRCIOD output level selected as “L” active
1: TRCIOD output level selected as “H” active
0: Count continues at compare match with the
1: Count stops at compare match with the TRCGRA
b7 b6
0 0: Disable the trigger input from the TRCTRG pin
0 1: Rising edge selected
1 0: Falling edge selected
1 1: Both edges selected
TRCGRA register
register
b3
—
1
POLD
b2
0
Function
POLC
b1
0
POLB
b0
0
19. Timer RC
R/W
R/W
R/W
R/W
R/W
R/W
R/W
—