R5F21274SDFP#U0 Renesas Electronics America, R5F21274SDFP#U0 Datasheet - Page 62
R5F21274SDFP#U0
Manufacturer Part Number
R5F21274SDFP#U0
Description
IC R8C/27 MCU FLASH 32LQFP
Manufacturer
Renesas Electronics America
Series
R8C/2x/27r
Datasheet
1.R5F21272SDFPU0.pdf
(487 pages)
Specifications of R5F21274SDFP#U0
Core Processor
R8C
Core Size
16/32-Bit
Speed
20MHz
Connectivity
I²C, LIN, SIO, SSU, UART/USART
Peripherals
LED, POR, Voltage Detect, WDT
Number Of I /o
25
Program Memory Size
16KB (16K x 8)
Program Memory Type
FLASH
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
2.2 V ~ 5.5 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
32-LQFP
For Use With
R0K521276S000BE - KIT DEV RSK-R8C/26-29R0E521000EPB00 - PROBE EMULATOR FOR PC7501
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
R5F21274SDFP#U0R5F21274SDFP#V2
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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R8C/26 Group, R8C/27 Group
Rev.2.10
REJ09B0278-0210
Figure 6.11
Voltage Monitor 1 Circuit Control Register
b7 b6 b5 b4
NOTES:
1.
2.
3.
4.
5.
6.
7.
Set the PRC3 bit in the PRCR register to 1 (rew rite enable) before w riting to the VW1C register.
To use the voltage monitor 1 interrupt to exit stop mode and to return again, w rite 0 to the VW1C1 bit before w riting
1.
The VW1C6 bit is enabled w hen the VW1C0 bit is set to 1 (voltage monitor 1 reset enabled).
The VW1C0 bit is enabled w hen the VCA26 bit in the VCA2 register is set to 1 (voltage detection 1 circuit enabled).
Set the VW1C0 bit to 0 (disable) w hen the VCA26 bit is set to 0 (voltage detection 1 circuit disabled).
The VW1C7 bit is enabled w hen the VW1C1 bit is set to 1 (digital filter disabled mode).
Softw are reset, w atchdog timer reset, or voltage monitor 2 reset do not affect this register.
When the VW1C6 bit is set to 1 (voltage monitor 1 reset mode), set the VW1C7 bit to 1 (w hen VCC reaches Vdet1 or
below ). (Do not set to 0.)
Sep 26, 2008
b3
b2
0
VW1C Register (J, K version)
b1 b0
Bit Symbol
VW1C0
VW1C6
VW1C7
VW1C1
VW1F0
VW1F1
Symbol
VW1C
(b2)
(b3)
Page 43 of 453
—
—
Voltage monitor 1 reset
enable bit
Voltage monitor 1 digital filter
disable mode select bit
Reserved bit
Reserved bit
Sampling clock select bits
Voltage monitor 1 circuit
mode select bit
Voltage monitor 1 reset
generation condition select
bit
(5, 7)
(4)
Address
Bit Name
0036h
(1)
(3)
(J, K Version)
(2)
b5 b4
0 0 : fOCO-S divided by 1
0 1 : fOCO-S divided by 2
1 0 : fOCO-S divided by 4
1 1 : fOCO-S divided by 8
The LVD1ON bit in the OFS register is
set to 1 and hardw are reset
Pow er-on reset, voltage monitor 1 reset
or LVD1ON bit in the OFS register is set
to 0, and hardw are reset
0 : Disable
1 : Enable
0 : Digital filter enabled mode
1 : Digital filter disabled mode
Set to 0.
When read, the content is undefined.
When the VW1C0 bit is 1(voltage monitor 1 reset
enabled), set to 1.
When the VW1C1 bit is 1(digital filter disabled
mode), set to 1.
(digital filter circuit enabled)
(digital filter circuit disabled)
After Reset
Function
(6)
6. Voltage Detection Circuit
: 0000X000b
: 0100X001b
RW
RW
RW
RW
RW
RW
RW
RW
RO
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