HD64F3672FPIV Renesas Electronics America, HD64F3672FPIV Datasheet - Page 182

• Manufacturer Part Number: HD64F3672FPIV
• Description: MCU 3/5V 16K I-TEMP PB-FREE 64-L
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300H Tinyr

Specifications of HD64F3672FPIV

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 16MHz
• Connectivity: SCI
• Peripherals: PWM, WDT
• Number Of I /o: 26
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-LQFP
• For Use With: R0K436079S000BE - KIT DEV FOR H8/36079 W/COMPILER
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 11 Timer W
11.6
The following types of contention or operation can occur in timer W operation.
1. The pulse width of the input clock signal and the input capture signal must be at least two
2. Writing to registers is performed in the T2 state of a TCNT write cycle.
3. Depending on the timing, TCNT may be incremented by a switch between different internal
4. If timer W enters module standby mode while an interrupt request is generated, the interrupt
Rev.4.00 Nov. 02, 2005 Page 156 of 304
REJ09B0143-0400
system clock ( ) cycles; shorter pulses will not be detected correctly.
If counter clear signal occurs in the T2 state of a TCNT write cycle, clearing of the counter
takes priority and the write is not performed, as shown in figure 11.24. If counting-up is
generated in the TCNT write cycle to contend with the TCNT counting-up, writing takes
precedence.
clock sources. When TCNT is internally clocked, an increment pulse is generated from the
rising edge of an internal clock signal, that is divided system clock ( ). Therefore, as shown in
figure 11.25 the switch is from a low clock signal to a high clock signal, the switchover is seen
as a rising edge, causing TCNT to increment.
request cannot be cleared. Before entering module standby mode, disable interrupt requests.
Usage Notes
Address
Write signal
Counter clear
signal
TCNT
Figure 11.24 Contention between TCNT Write and Clear
TCNT write cycle
N
TCNT address
T1
T2
H'0000