MC68HC705C8AFNE Freescale Semiconductor, MC68HC705C8AFNE Datasheet - Page 80

• Manufacturer Part Number: MC68HC705C8AFNE
• Description: IC MCU 8BIT 44-PLCC
• Manufacturer: Freescale Semiconductor
• Series: HC05r

Specifications of MC68HC705C8AFNE

• Core Processor: HC05
• Core Size: 8-Bit
• Speed: 2.1MHz
• Connectivity: SCI, SPI
• Peripherals: POR, WDT
• Number Of I /o: 24
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: OTP
• Ram Size: 304 x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 44-PLCC
• Processor Series: HC705C
• Core: HC05
• Data Bus Width: 8 bit
• Data Ram Size: 304 B
• Interface Type: SCI, SPI
• Maximum Clock Frequency: 2.1 MHz
• Number Of Programmable I/os: 24
• Number Of Timers: 1
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: 0 C
• On-chip Adc: 8 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

Parallel Input/Output (I/O)
7.3.3 Port A Logic
Technical Data
80
NOTE:
Figure 7-3
When a port A pin is programmed to be an output, the state of its data
register bit determines the state of the output pin. When a port A pin is
programmed to be an input, reading the port A data register returns the
logic state of the pin.
The data latch can always be written, regardless of the state of its DDRA
bit.
To avoid excessive current draw, tie all unused input pins to V
or change I/O pins to outputs by writing to DDRA in user code as early
as possible.
1. Hi-Z = high impedance
2. Writing affects data register but does not affect input.
DDRA Bit
Freescale Semiconductor, Inc.
Table 7-1
For More Information On This Product,
0
1
READ $0004
WRITE $0004
WRITE $0000
READ $0000
is a diagram of the port A I/O logic.
Go to: www.freescale.com
Parallel Input/Output (I/O)
I/O Pin Mode
Input, Hi-Z
summarizes the operation of the port A pins.
RESET
Output
Table 7-1. Port A Pin Functions
Figure 7-3. Port A I/O Logic
(1)
DATA DIRECTION
PORT A DATA
REGISTER A
REGISTER
BIT DDRAx
BIT PAx
Accesses to DDRA
DDRA7–DDRA0
DDRA7–DDRA0
Read/Write
MC68HC705C8A — Rev. 3
PA7–PA0
Accesses to PORTA
Read
Pin
PA7–PA0
DD
PA7–PA0
Write
or V
PAx
SS
(2)
,