HD64F3687FPIV Renesas Electronics America, HD64F3687FPIV Datasheet - Page 78

MCU 3/5V 56K I-TEMP PB-FREE 64-L

HD64F3687FPIV

Manufacturer Part Number
HD64F3687FPIV
Description
MCU 3/5V 56K I-TEMP PB-FREE 64-L
Manufacturer
Renesas Electronics America
Series
H8® H8/300H Tinyr
Datasheet

Specifications of HD64F3687FPIV

Core Processor
H8/300H
Core Size
16-Bit
Speed
20MHz
Connectivity
I²C, SCI
Peripherals
PWM, WDT
Number Of I /o
45
Program Memory Size
56KB (56K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-LQFP
For Use With
R0K436079S000BE - KIT DEV FOR H8/36079 W/COMPILER
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
HD64F3687FPIV
Manufacturer:
RENESAS/瑞萨
Quantity:
20 000
Section 2 CPU
Bit Manipulation in a Register Containing a Write-Only Bit
Example 3: BCLR instruction executed designating port 5 control register PCR5
P57 and P56 are input pins, with a low-level signal input at P57 and a high-level signal input at
P56. P55 to P50 are output pins that output low-level signals. An example of setting the P50 pin as
an input pin by the BCLR instruction is shown below. It is assumed that a high-level signal will be
input to this input pin.
Rev.5.00 Nov. 02, 2005 Page 44 of 500
REJ09B0027-0500
Input/output
Pin state
PCR5
PDR5
RAM0
Input/output
Pin state
PCR5
PDR5
RAM0
MOV.B
MOV.B
MOV.B
BSET
MOV.B
MOV.B
Prior to executing BSET instruction
BSET instruction executed
After executing BSET instruction
#80,
R0L,
R0L,
#0,
@RAM0, R0L
R0L,
P57
Input
Low
level
0
1
1
P57
Input
Low
level
0
1
1
R0L
@RAM0
@PDR5
@PDR5
@RAM0
P56
Input
High
level
0
0
0
P56
Input
High
level
0
0
0
P55
Output
Low
level
1
0
0
P55
Output
Low
level
1
0
0
The PDR5 value (H'80) is written to a work area in
memory (RAM0) as well as to PDR5.
The BSET instruction is executed designating the PDR5
work area (RAM0).
The work area (RAM0) value is written to PDR5.
P54
Output
Low
level
1
0
0
P54
Output
Low
level
1
0
0
P53
Output
Low
level
1
0
0
P53
Output
Low
level
1
0
0
P52
Output
Low
level
1
0
0
P52
Output
Low
level
1
0
0
P51
Output
1
0
0
P51
Output
1
0
0
Low
level
Low
level
P50
Output
Low
level
1
0
0
P50
Output
High
level
1
1
1

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