MC68331MEH16 Freescale Semiconductor, MC68331MEH16 Datasheet - Page 12

• Manufacturer Part Number: MC68331MEH16
• Description: IC MCU 32BIT 16MHZ 132-PQFP
• Manufacturer: Freescale Semiconductor
• Series: M683xxr

Specifications of MC68331MEH16

• Core Processor: CPU32
• Core Size: 32-Bit
• Speed: 16MHz
• Connectivity: EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 18
• Program Memory Type: ROMless
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 132-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Ram Size: -
• Program Memory Size: -
• Data Converters: -

12
Boot Chip Select
Data Bus
Data Strobe
Data and Size Acknowledge
Development Serial In, Out,
Clock
Crystal Oscillator
Function Codes
Freeze
Halt
Input Capture
Input Capture 4/Output Compare
5
Instruction Pipeline
Interrupt Request Level
Master In Slave Out
Clock Mode Select
Master Out Slave In
Output Compare
Pulse Accumulator Input
Port C
Auxiliary Timer Clock Input
Peripheral Chip Select
Port E
Port F
Port QS
Pulse-Width Modulation
Quotient Out
Reset
Read-Modify-Write Cycle
Read/Write
SCI Receive Data
QSPI Serial Clock
Size
Slave Select
Three-State Control
SCI Transmit Data
External Filter Capacitor
Signal Name
Freescale Semiconductor, Inc.
For More Information On This Product,
Table 6 MCU Signal Function (Continued)
PWMA, PWMB Output for PWM
IPIPE, IFETCH Indicate instruction pipeline activity
EXTAL, XTAL Connections for clock synthesizer circuit reference;
DSACK[1:0]
DATA[15:0]
Mnemonic
DSI, DSO,
MODCLK
CSBOOT
PCS[3:0]
PQS[7:0]
FREEZE
IC4/OC5
IRQ[7:1]
OC[5:1]
SIZ[1:0]
DSCLK
PC[6:0]
RESET
FC[2:0]
PE[7:0]
PF[7:0]
IC[3:1]
QUOT
PCLK
HALT
MISO
MOSI
RMC
RXD
SCK
R/W
TSC
TXD
XFC
PAI
DS
SS
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Chip select for external boot startup ROM
16-bit data bus
During a read cycle, indicates when it is possible for an external
device to place data on the data bus. During a write cycle, indi-
cates that valid data is on the data bus.
Provide asynchronous data transfers and dynamic bus sizing
Serial I/O and clock for background debugging mode
a crystal or an external oscillator can be used
Identify processor state and current address space
Indicates that the CPU has entered background mode
Suspend external bus activity
When a specified transition is detected on an input capture pin, the
value in an internal GPT counter is latched
Can be configured for either an input capture or output compare
Provides an interrupt priority level to the CPU
Serial input to QSPI in master mode;
serial output from QSPI in slave mode
Selects the source and type of system clock
Serial output from QSPI in master mode;
serial input to QSPI in slave mode
Change state when the value of an internal GPT counter matches
a value stored in a GPT control register
Signal input to the pulse accumulator
SIM digital output port signals
External clock dedicated to the GPT
QSPI peripheral chip selects
SIM digital I/O port signals
SIM digital I/O port signals
QSM digital I/O port signals
Provides the quotient bit of the polynomial divider
System reset
Indicates an indivisible read-modify-write instruction
Indicates the direction of data transfer on the bus
Serial input to the SCI
Clock output from QSPI in master mode;
clock input to QSPI in slave mode
Indicates the number of bytes to be transferred during a bus cycle
Causes serial transmission when QSPI is in slave mode;
causes mode fault in master mode
Places all output drivers in a high-impedance state
Serial output from the SCI
Connection for external phase-locked loop filter capacitor
Function
MC68331TS/D