D17760BP200ADV Renesas Electronics America, D17760BP200ADV Datasheet - Page 1046

• Manufacturer Part Number: D17760BP200ADV
• Description: MPU 3V 8K,PB-FREE, 256-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of D17760BP200ADV

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 69
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

• INTSTR2
Rev. 2.00 Feb. 12, 2010 Page 962 of 1330
REJ09B0554-0200
Bit
7 to 2
1
0
Bit
Name
⎯
FRDY
_TU
FRDYI
Initial
Value
All 0
⎯
0
Initial value:
R/W:
Bit:
R/W
R
R
R/W
R
7
-
0
6
0
R
-
Description
Reserved
These bits are always read as 0. The write
value should always be 0.
FIFO Ready Flag
Regardless of set values of DMAEN and
FRDYIE, this bit is read as 0 when FIFO
data amount matches the condition set in
DMACR[2:0], and otherwise, read as 1.
FIFO Ready Interrupt
0: No interrupt
[Clearing condition]
Write 0 after reading FRDYI = 1.
1: Interrupt requested
[Setting condition]
When remained FIFO data does not
match the assert condition set in DMACR
while DMAEN = 1 and FRDYIE = 1.
Note: FRDYI will be set on the setting
R
5
0
-
condition after clearing. To clear it,
disable the flag setting by FRDYIE
in INTCR2.
4
0
-
R
R
3
-
0
2
R
-
0
FRDY
_TU
R
1
-
FRDYI
R/W
0
0
Interrupt
outputs
⎯
⎯
MMCI3