D17760BP200ADV Renesas Electronics America, D17760BP200ADV Datasheet - Page 253

• Manufacturer Part Number: D17760BP200ADV
• Description: MPU 3V 8K,PB-FREE, 256-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of D17760BP200ADV

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 69
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

2. IC address array write (non-associative)
3. IC address array write (associative)
7.5.2
The IC data array is allocated to addresses H'F100 0000 to H'F1FF FFFF in the P4 area. A data
array access requires a 32-bit address field specification (when reading or writing) and a 32-bit
data field specification. The entry to be accessed is specified in the address field, and the longword
data to be written is specified in the data field.
In the address field, bits [31:24] have the value H'F1 indicating the IC data array, and the entry is
specified by bits [12:5]. The IIX bit in CCR has no effect on this entry specification. Address field
bits [4:2] are used for the longword data specification in the entry. As only longword access is
used, 0 should be specified for address field bits [1:0].
The data field is used for the longword data specification.
The tag and V bit specified in the data field are written to the IC entry corresponding to the
entry set in the address field. The A bit in the address field should be cleared to 0.
When a write is performed with the A bit in the address field set to 1, the tag stored in the entry
specified in the address field is compared with the tag specified in the data field. If the MMU
is enabled at this time, comparison is performed after the virtual address specified by data field
bits [31:10] has been translated to a physical address using the ITLB. If the addresses match
and the V bit is 1, the V bit specified in the data field is written into the IC entry. In other
cases, no operation is performed. This operation is used to invalidate a specific IC entry. If an
ITLB miss occurs during address translation, or the comparison shows a mismatch, an
exception is not generated, no operation is performed, and the write is not executed. If an
instruction TLB multiple hit exception occurs during address translation, processing switches
to the instruction TLB multiple hit exception handling routine.
IC Data Array
Address field
Data field
31
31
V
A
1 1 1 1 0 0 0 0
Figure 7.5 Memory-Mapped IC Address Array
: Validity bit
: Association bit
: Reserved bits (write value should be 0, and read value is undefined )
24
23
Tag
13
Rev. 2.00 Feb. 12, 2010 Page 169 of 1330
12
10 9
Entry
5 4 3 2 1 0
A
REJ09B0554-0200
1 0
V