MAXQ3108-FFN+ Maxim Integrated Products, MAXQ3108-FFN+ Datasheet - Page 49

• Manufacturer Part Number: MAXQ3108-FFN+
• Description: IC MCU DUAL-CORE 16BIT 28-TSSOP
• Manufacturer: Maxim Integrated Products
• Series: MAXQ™r

Specifications of MAXQ3108-FFN+

• Core Processor: RISC
• Core Size: 16-Bit
• Speed: 10MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 21
• Program Memory Size: 64KB (32K x 16)
• Program Memory Type: FLASH
• Ram Size: 11K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-TSSOP
• Processor Series: MAXQ
• Core: RISC
• Data Bus Width: 16 bit
• Data Ram Size: 2 KB
• Interface Type: I2C, JTAG, SPI
• Maximum Clock Frequency: 10 MHz
• Number Of Programmable I/os: 22
• Number Of Timers: 2
• Operating Supply Voltage: 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

I2CCN.7: I2CSTOP
I2CCN.8: I2CGCEN
I2CCN.9: I2CSTREN
I2CCN.[14:10]: Reserved
I2CCN.15: I2CRST
I2CCK (0Dh, 04h)
Initialization:
Read/Write Access:
I2CCK.[7:0]: I2CCKL[7:0]
I2CCK.[15:8]: I2CCKH[7:0]
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Low-Power, Dual-Core Microcontroller
I
cleared to 0 after the STOP condition has been generated. In master mode, setting this bit could
also start the timeout timer if enabled. If the timeout timer expires before the STOP condition can be
generated, a timeout interrupt is generated to the CPU if enabled. The I2CSTOP bit is also cleared
to 0 by the timeout event.
Note that this bit has no effect when the I
to 0 when I2CMST = 0 or I2CEN = 0. Setting the I2CSTOP bit to 1 while I2CSTART = 1 is an invalid
operation and is ignored, leaving the I2CSTOP bit cleared to 0.
I
address (address = 0000 0000). Clearing this bit to 0 disables the response to a general call
address.
I
clock cycle specified in I2CSTRS. Clearing this bit disables clock stretching.
Reserved. Reads return 0.
I
set to 1 by software and is only cleared to 0 by hardware after the reset or when I2CEN = 0.
I
This register is set to 0204h on all forms of reset.
Unrestricted read. Write to this register is allowed only when I2CBUSY = 0. This register has no
function when operating in slave mode and the clock generation circuitry should be disabled.
I
with bit 7 as the most significant bit. The duration of SCL low time is calculated using the following
equation:
When operating in master mode, the I2CCKL must be set to a minimum value of four to ensure
proper operation. Any value less than four is set to four.
I
with bit 7 as the most significant bit. The duration of SCL high time is calculated using the
following equation:
When operating in master mode, the I2CCKH must be set to a minimum value of two to ensure
proper operation. Any value less than two is set to two.
2
2
2
2
2
2
2
C STOP Enable. Setting this bit to 1 generates a STOP condition. This bit is automatically self-
C General Call Enable. Setting this bit to 1 enables the I
C Clock Stretch Enable. Setting this bit to 1 stretches the clock (hold SCL low) at the end of the
C Reset. Setting this bit to 1 aborts the current transaction and resets the I
C Clock Control Register (16-Bit Register)
C Clock Low Bits 7:0. These bits define the I
C Clock High Bits 7:0. These bits define the I
Special Function Register Bit Descriptions (continued)
I
I
2
2
C High Time Period = System Clock x (I2CCKH[7:0] + 1)
C Low Time Period = System Clock x (I2CCKL[7:0] + 1)
2
C is operating in slave mode (I2CMST = 0) and is reset
2
2
C SCL low period in a number of system clocks,
C SCL high period in a number of system clocks,
2
C bus to respond to a general call
2
C controller. This bit is
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