MAXQ3108-FFN+ Maxim Integrated Products, MAXQ3108-FFN+ Datasheet - Page 55

• Manufacturer Part Number: MAXQ3108-FFN+
• Description: IC MCU DUAL-CORE 16BIT 28-TSSOP
• Manufacturer: Maxim Integrated Products
• Series: MAXQ™r

Specifications of MAXQ3108-FFN+

• Core Processor: RISC
• Core Size: 16-Bit
• Speed: 10MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 21
• Program Memory Size: 64KB (32K x 16)
• Program Memory Type: FLASH
• Ram Size: 11K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-TSSOP
• Processor Series: MAXQ
• Core: RISC
• Data Bus Width: 16 bit
• Data Ram Size: 2 KB
• Interface Type: I2C, JTAG, SPI
• Maximum Clock Frequency: 10 MHz
• Number Of Programmable I/os: 22
• Number Of Timers: 2
• Operating Supply Voltage: 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

active mode. The power monitor invokes a brownout
reset state to halt program execution when V
below the threshold condition. This ensures that the
microcontroller is safely placed into a reset state when-
ever V
tion while the supply voltage is too low. When power
returns above the reset threshold, and once the internal
POR delay (65,536 FLL cycles) is satisfied, the device
is initialized just as though power was removed and
reapplied.
The processor exits the reset condition automatically
once V
Software can determine that a power-on reset has
occurred by checking the power-on reset (POR) flag in
the WDCN register. Software should clear the POR bit
after reading it.
The brownout detect function can be disabled during
stop mode using the brownout disable (BOD) bit in the
PWCN register. The POR default state for the BOD bit is
0, which enables the brownout detect function during
stop mode. If brownout detection is disabled during
stop mode, the circuitry responsible for detecting a
brownout condition is shut down and the V
condition does not invoke the reset state. Since func-
tionality of the device is not guaranteed when
V
that the supply voltage is above the minimum operating
voltage range (V
ing stop mode.
The watchdog timer is a free-running programmable
timer. The watchdog supervises the processor opera-
tion by requiring software to clear the timer counter
before the timeout expires. If the timer is enabled and
software fails to clear it before this interval expires, the
device is placed into a reset state. The reset state
maintains for nine system clock cycles. Once the reset
is removed, the processor resumes execution at
address 8000h. Software can determine if a reset is
caused by a watchdog timeout by checking the watch-
dog timer reset flag, WTRF, in the WDCN register. This
flag must be cleared by software.
If the RST input is taken to logic 0, the device is forced
into a reset state. An external reset is accomplished by
holding the RST pin low at least four clock cycles while
the oscillator/FLL oscillator is running. Once the reset
state is invoked, it is maintained as long as RST is
pulled to logic 0. When the RST pin is released to return
to a high state, the processor exits the reset state within
DD
< V
DD
DD
RST
< V
meets the minimum voltage requirement.
, it is the responsibility of the user to ensure
RST
, thus preventing possible code execu-
RST
______________________________________________________________________________________
) defined for the device when exit-
Low-Power, Dual-Core Microcontroller
Watchdog Timer Reset
External Reset
DD
DD
< V
drops
RST
12 clock cycles and begins execution at address
8000h.
If a reset state is applied while the processor is in stop
mode, the reset causes the processor to exit the stop
mode and forces the program counter to 8000h.
The external reset (RST) pin function on the MAXQ3108
can be disabled by user application code. The power-
on-reset default condition is for the RST pin to be
enabled. Some applications, however, may not use the
reset input function or may use the alternate function
assigned to the pin. The reset function on the external
pin can be disabled by setting the RSTD bit of the
PWCN register to a logic 1. Since the POR default con-
dition for the device results in the RST function being
enabled on the pin, users should be cautioned that
holding the pin low on power-up prevents exiting of the
reset state and the ability to execute the code neces-
sary to disable the RST function. When the reset func-
tion is enabled on the RST pin, user code can generate
a reset by writing a 0 to the port pin.
The MAXQ3108 contains three GPIO ports: P0, P1, and
P2. Internally, each of these ports is 8 bits wide; howev-
er, not all bits of all ports are connected to pins. Port P0
exposes bits 0 to 7, port P1 exposes bits 0 to 6, and
port P2 exposes bits 0 to 5. Writes to unused bits have
no effect. Reads from unused bits could be in an inde-
terminate state.
For information on using GPIO ports, refer to Section 6
of the MAXQ Family User’s Guide .
The MAXQ3108 contains two UARTs (universal syn-
chronous/asynchronous receiver/transmitters). Most
often, these are used as standard asynchronous serial
ports for console applications; however, they are quite
flexible and can be used in a variety of ways.
Each port can be configured through the control regis-
ter (SCONx) and the mode register (SMDx). The baud
rate is established by programming an appropriate
value in the phase register (PRx). Finally, communica-
tion is performed by writing and reading the buffer reg-
ister (SBUFx).
Details on using these ports can be found in Section 10
of the MAXQ Family User’s Guide . Note that the multi-
processor support mentioned in this document is not
supported by the serial ports implemented in the
MAXQ3108.
Reset Input Pin Disable
Peripheral Devices
GPIO Ports
UARTs
55