SAK-XC2365B-40F80L AA Infineon Technologies, SAK-XC2365B-40F80L AA Datasheet - Page 41

• Manufacturer Part Number: SAK-XC2365B-40F80L AA
• Description: IC MCU 16BIT 320KB FLASH 100LQFP
• Manufacturer: Infineon Technologies
• Series: XC23xxBr

Specifications of SAK-XC2365B-40F80L AA

• Core Processor: C166SV2
• Core Size: 16/32-Bit
• Speed: 80MHz
• Connectivity: CAN, EBI/EMI, I²C, LIN, SPI, SSC, UART/USART, USI
• Peripherals: I²S, POR, PWM, WDT
• Number Of I /o: 76
• Program Memory Size: 320KB (320K x 8)
• Program Memory Type: FLASH
• Ram Size: 34K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 100-LSQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

Table 8
Address Area
Reserved for DSRAM
External memory area
1) Accesses to the shaded areas are reserved. In devices with external bus interface these accesses generate
2) The areas marked with “<” are slightly smaller than indicated, see column “Notes”.
3) The uppermost 4-Kbyte sector of the first Flash segment is reserved for internal use (C0’F000
4) Several pipeline optimizations are not active within the external IO area. This is necessary to control external
This common memory space consists of 16 Mbytes organized as 256 segments of
64 Kbytes; each segment contains four data pages of 16 Kbytes. The entire memory
space can be accessed bytewise or wordwise. Portions of the on-chip DPRAM and the
register spaces (ESFR/SFR) additionally are directly bit addressable.
The internal data memory areas and the Special Function Register areas (SFR and
ESFR) are mapped into segment 0, the system segment.
The Program Management Unit (PMU) handles all code fetches and, therefore, controls
access to the program memories such as Flash memory and PSRAM.
The Data Management Unit (DMU) handles all data transfers and, therefore, controls
access to the DSRAM and the on-chip peripherals.
Both units (PMU and DMU) are connected to the high-speed system bus so that they can
exchange data. This is required if operands are read from program memory, code or
data is written to the PSRAM, code is fetched from external memory, or data is read from
or written to external resources. These include peripherals on the LXBus such as USIC
or MultiCAN. The system bus allows concurrent two-way communication for maximum
transfer performance.
Up to 16 Kbytes of on-chip Program SRAM (PSRAM) are provided to store user code
or data. The PSRAM is accessed via the PMU and is optimized for code fetches. A
section of the PSRAM with programmable size can be write-protected.
Note: The actual size of the PSRAM depends on the quoted device type.
Data Sheet
external bus accesses.
peripherals properly.
XC236xB Memory Map (cont’d)
Start Loc. End Loc.
00’8000
00’0000
H
H
00’9FFF
00’7FFF
XC2361B, XC2363B, XC2364B, XC2365B
41
1)
H
H
Area Size
8 Kbytes
32 Kbytes
XC2000 Family / Value Line
2)
Functional Description
Notes
V1.2, 2010-04
H
to C0’FFFF
H
).