SAF-XE167F-96F80L AC Infineon Technologies, SAF-XE167F-96F80L AC Datasheet - Page 50

• Manufacturer Part Number: SAF-XE167F-96F80L AC
• Description: IC MCU 16BIT FLASH 144-LQFP
• Manufacturer: Infineon Technologies
• Series: XE16xr

Specifications of SAF-XE167F-96F80L AC

• Core Processor: C166SV2
• Core Size: 16-Bit
• Speed: 80MHz
• Connectivity: CAN, EBI/EMI, I²C, LIN, SPI, SSC, UART/USART, USI
• Peripherals: I²S, POR, PWM, WDT
• Number Of I /o: 118
• Program Memory Size: 768KB (768K x 8)
• Program Memory Type: FLASH
• Ram Size: 82K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 24x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LFQFP
• Data Bus Width: 16 bit
• Data Ram Size: 64 KB
• Interface Type: CAN
• Maximum Clock Frequency: 66 MHz
• Number Of Programmable I/os: 118
• Number Of Timers: 11
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 24 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: SP000450816

The XE167 includes an excellent mechanism to identify and process exceptions or error
conditions that arise during run-time, the so-called ‘Hardware Traps’. A hardware trap
causes an immediate non-maskable system reaction similar to a standard interrupt
service (branching to a dedicated vector table location). The occurrence of a hardware
trap is also indicated by a single bit in the trap flag register (TFR). Unless another higher-
priority trap service is in progress, a hardware trap will interrupt any ongoing program
execution. In turn, hardware trap services can normally not be interrupted by standard
or PEC interrupts.
Table 7
Table 7
Exception Condition
Reset Functions
Class A Hardware Traps:
•
•
•
•
Class B Hardware Traps:
•
•
•
•
•
Reserved
Software Traps:
•
1) Register VECSEG defines the segment where the vector table is located to.
Data Sheet
Bitfield VECSC in register CPUCON1 defines the distance between two adjacent vectors. This table
represents the default setting, with a distance of 4 (two words) between two vectors.
System Request 0
Stack Overflow
Stack Underflow
Software Break
System Request 1
Undefined Opcode
Memory Access Error
Protected Instruction
Fault
Illegal Word Operand
Access
TRAP Instruction
shows all possible exceptions or error conditions that can arise during runtime:
Trap Summary
Trap
Flag
–
SR0
STKOF
STKUF
SOFTBRK
SR1
UNDOPC
ACER
PRTFLT
ILLOPA
–
–
Trap
Vector
RESET
SR0TRAP
STOTRAP
STUTRAP
SBRKTRAP
BTRAP
BTRAP
BTRAP
BTRAP
BTRAP
–
–
48
Vector
Location
xx’0000
xx’0008
xx’0010
xx’0018
xx’0020
xx’0028
xx’0028
xx’0028
xx’0028
xx’0028
[2C
Any
[xx’0000
xx’01FC
in steps of
4
XE166 Family Derivatives
H
H
- 3C
Functional Description
H
H
H
H
H
H
H
H
H
H
H
H
1)
]
H
-
] [0B
Trap
Number
00
02
04
06
08
0A
0A
0A
0A
0A
0F
Any
[00
7F
H
H
H
H
H
H
H
H
H
H
H
H
H
H
]
]
-
-
V2.1, 2008-08
XE167x
Trap
Priority
III
II
II
II
II
I
I
I
I
I
–
Current
CPU
Priority