SAK-TC1767-256F133HL AD Infineon Technologies, SAK-TC1767-256F133HL AD Datasheet - Page 52

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SAK-TC1767-256F133HL AD

Manufacturer Part Number
SAK-TC1767-256F133HL AD
Description
IC MCU 32BIT FLASH 176-LQFP
Manufacturer
Infineon Technologies
Series
TC17xxr
Datasheet

Specifications of SAK-TC1767-256F133HL AD

Core Processor
TriCore
Core Size
32-Bit
Speed
133MHz
Connectivity
ASC, CAN, MLI, MSC, SSC
Peripherals
DMA, POR, WDT
Number Of I /o
88
Program Memory Size
2MB (2M x 8)
Program Memory Type
FLASH
Ram Size
128K x 8
Voltage - Supply (vcc/vdd)
1.42 V ~ 1.58 V
Data Converters
A/D 4x10b, 32x12b
Oscillator Type
External
Operating Temperature
-40°C ~ 125°C
Package / Case
176-LFQFP
Data Bus Width
32 bit
Data Ram Size
92 KB
Interface Type
SPI
Maximum Clock Frequency
133 MHz
Number Of Programmable I/os
88
Number Of Timers
2
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
2 (12 bit, 16 Channel)
Packages
PG-LQFP-176
Max Clock Frequency
133.0 MHz
Sram (incl. Cache)
128.0 KByte
Can Nodes
2
A / D Input Lines (incl. Fadc)
36
Program Memory
2.0 MB
For Use With
B158-H8539-G2-X-7600IN - KIT STARTER TC176X SERIES
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
 Details
Other names
SP000458056
FADC Power Supply and References
The FADC module is supplied by the following power supply and reference voltage lines:
Input Structure
The input structure of the FADC in the TC1767 contains:
Data Sheet
An A/D Converter Stage responsible for the analog-to-digital conversion including an
input multiplexer to select between the channel amplifiers
A Data Reduction Unit containing programmable anti-aliasing and data reduction
filters
A Channel Trigger Control block determining the trigger and gating conditions for the
FADC channels
A Channel Timer for each channel to independently trigger the conversions
An A/D Control block responsible for the overall FADC functionality
V
V
the V
the V
V
to be fed in externally
V
A differential analog input stage for each input channel to select the input impedance
(differential or single-ended measurement) and to decouple the FADC input signal
from the pins.
A channel amplifier for each input channel with a settling time (about 5µs) when
changing the characteristics of an input stage (changing between unused,
differential, single-ended N, or single-ended P mode).
DDMF
DDIF
DDAF
FAREF
DDIF
DDM
/ V
/ V
/ V
/ V
SSMF
SSAF
SSMF
supply does not appear as supply pin, because it is internally connected to
supply of the ADC that is sharing the FADC input pins.
FAGND
: FADC Analog Input Stage Power Supply (3.3 - 5 V),
: FADC Analog Part Power Supply (1.5 V),
: FADC Analog Channel Amplifier Power Supply (3.3 V)
: FADC Reference Voltage (3.3 V max.) and FADC Reference Ground
48
Introduction
V1.3, 2009-09
TC1767

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