ATMEGA8L-8AC Atmel, ATMEGA8L-8AC Datasheet - Page 210

• Manufacturer Part Number: ATMEGA8L-8AC
• Description: IC AVR MCU 8K LV 8MHZ COM 32TQFP
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA8L-8AC

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 23
• Program Memory Size: 8KB (4K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 32-TQFP, 32-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: ATMEGA8L8AC

EEPROM Write
Prevents Writing to
SPMCR
Reading the Fuse and
Lock Bits from
Software
Preventing Flash
Corruption
210
ATmega8(L)
See
Loader Bits affect the Flash access.
If bits 5..2 in R0 are cleared (zero), the corresponding Boot Lock bit will be programmed if an
SPM instruction is executed within four cycles after BLBSET and SPMEN are set in SPMCR.
The Z-pointer is don’t care during this operation, but for future compatibility it is recommended to
load the Z-pointer with 0x0001 (same as used for reading the Lock Bits). For future compatibility
It is also recommended to set bits 7, 6, 1, and 0 in R0 to “1” when writing the Lock Bits. When
programming the Lock Bits the entire Flash can be read during the operation.
Note that an EEPROM write operation will block all software programming to Flash. Reading the
Fuses and Lock Bits from software will also be prevented during the EEPROM write operation. It
is recommended that the user checks the status bit (EEWE) in the EECR Register and verifies
that the bit is cleared before writing to the SPMCR Register.
It is possible to read both the Fuse and Lock Bits from software. To read the Lock Bits, load the
Z-pointer with 0x0001 and set the BLBSET and SPMEN bits in SPMCR. When an LPM instruc-
tion is executed within three CPU cycles after the BLBSET and SPMEN bits are set in SPMCR,
the value of the Lock Bits will be loaded in the destination register. The BLBSET and SPMEN
bits will auto-clear upon completion of reading the Lock Bits or if no LPM instruction is executed
within three CPU cycles or no SPM instruction is executed within four CPU cycles. When BLB-
SET and SPMEN are cleared, LPM will work as described in the
The algorithm for reading the Fuse Low bits is similar to the one described above for reading the
Lock Bits. To read the Fuse Low bits, load the Z-pointer with 0x0000 and set the BLBSET and
SPMEN bits in SPMCR. When an LPM instruction is executed within three cycles after the BLB-
SET and SPMEN bits are set in the SPMCR, the value of the Fuse Low bits (FLB) will be loaded
in the destination register as shown below. Refer to
tion and mapping of the fuse low bits.
Similarly, when reading the Fuse High bits, load 0x0003 in the Z-pointer. When an LPM instruc-
tion is executed within three cycles after the BLBSET and SPMEN bits are set in the SPMCR,
the value of the Fuse High bits (FHB) will be loaded in the destination register as shown below.
Refer to
Fuse and Lock Bits that are programmed, will be read as zero. Fuse and Lock Bits that are
unprogrammed, will be read as one.
During periods of low V
low for the CPU and the Flash to operate properly. These issues are the same as for board level
systems using the Flash, and the same design solutions should be applied.
A Flash program corruption can be caused by two situations when the voltage is too low. First, a
regular write sequence to the Flash requires a minimum voltage to operate correctly. Secondly,
the CPU itself can execute instructions incorrectly, if the supply voltage for executing instructions
is too low.
Bit
Rd
Bit
Rd
Bit
Rd
Table 78 on page 205
Table 87 on page 216
FLB7
FHB7
7
7
7
–
FHB6
FLB6
CC,
6
6
6
–
the Flash program can be corrupted because the supply voltage is too
and
BLB12
FHB5
FLB5
for detailed description and mapping of the fuse high bits.
Table 79 on page 205
5
5
5
BLB11
FHB4
FLB4
4
4
4
BLB02
FHB3
FLB3
3
3
3
Table 88 on page 217
for how the different settings of the Boot
BLB01
FLB2
FHB2
2
2
2
FHB1
Instruction set
FLB1
LB2
1
1
1
FHB0
FLB0
LB1
for a detailed descrip-
0
0
0
Manual.
2486Z–AVR–02/11