ATMEGA8L-8AC Atmel, ATMEGA8L-8AC Datasheet - Page 239

• Manufacturer Part Number: ATMEGA8L-8AC
• Description: IC AVR MCU 8K LV 8MHZ COM 32TQFP
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA8L-8AC

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 23
• Program Memory Size: 8KB (4K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 32-TQFP, 32-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: ATMEGA8L8AC

SPI Timing
Characteristics
2486Z–AVR–02/11
5. This requirement applies to all ATmega8 Two-wire Serial Interface operation. Other devices connected to the Two-wire Serial
6. The actual low period generated by the ATmega8 Two-wire Serial Interface is (1/f
7. The actual low period generated by the ATmega8 Two-wire Serial Interface is (1/f
Bus need only obey the general f
6MHz for the low time requirement to be strictly met at f
will not be strictly met for f
full speed (400kHz) with other ATmega8 devices, as well as any other device with a proper t
Figure 115. Two-wire Serial Bus Timing
See
Table 102. SPI Timing Parameters
Note:
10
11
12
13
14
15
16
17
18
1
2
3
4
5
6
7
8
9
SCL
SDA
Figure 116 on page 240
SCL
1. In SPI Programming mode the minimum SCK high/low period is:
SS high to tri-state
t
SU;STA
> 308kHz when f
SCK to out high
SCK to SS high
- 2t
- 3t
SCK high/low
SS low to SCK
SCK high/low
Rise/Fall time
Rise/Fall time
SS low to out
Description
SCK period
Out to SCK
SCK period
SCK to out
SCK to out
CLCL
CLCL
SCL
Setup
Setup
Hold
Hold
requirement
for f
for f
CK
CK
(1)
< 12MHz
> 12MHz
t
CK
HD;STA
= 8MHz. Still, ATmega8 devices connected to the bus may communicate at
t
and
of
t
LOW
Master
Master
Master
Master
Master
Master
Master
Master
Figure 117 on page 240
Mode
Slave
Slave
Slave
Slave
Slave
Slave
Slave
Slave
Slave
Salve
SCL
= 100kHz
t
HIGH
t
HD;DAT
4 • t
2 • t
2 • t
Min
10
10
20
ck
ck
ck
t
LOW
See
t
50% duty cycle
SU;DAT
SCL
page 126
SCL
for details.
0.5 • t
Table 50 on
Typ
3.6
10
10
10
10
15
15
10
- 2/f
- 2/f
SCK
CK
CK
), thus the low time requirement
), thus f
LOW
acceptance margin
ATmega8(L)
CK
Max
1600
t
SU;STO
must be greater than
t
r
ns
t
BUF
239