ATMEGA8L-8AC Atmel, ATMEGA8L-8AC Datasheet - Page 230

• Manufacturer Part Number: ATMEGA8L-8AC
• Description: IC AVR MCU 8K LV 8MHZ COM 32TQFP
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA8L-8AC

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 23
• Program Memory Size: 8KB (4K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 32-TQFP, 32-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: ATMEGA8L8AC

Serial
Downloading
Serial
Programming Pin
Mapping
230
ATmega8(L)
Both the Flash and EEPROM memory arrays can be programmed using the serial SPI bus while
RESET is pulled to GND. The serial interface consists of pins SCK, MOSI (input) and MISO (out-
put). After RESET is set low, the Programming Enable instruction needs to be executed first
before program/erase operations can be executed. NOTE, in
programming is listed. Not all parts use the SPI pins dedicated for the internal SPI interface.
Table 96. Pin Mapping Serial Programming
Figure 112. Serial Programming and Verify
Notes:
When programming the EEPROM, an auto-erase cycle is built into the self-timed programming
operation (in the Serial mode ONLY) and there is no need to first execute the Chip Erase
instruction. The Chip Erase operation turns the content of every memory location in both the
Program and EEPROM arrays into 0xFF.
Depending on CKSEL Fuses, a valid clock must be present. The minimum low and high periods
for the Serial Clock (SCK) input are defined as follows:
Low:> 2 CPU clock cycles for f
High:> 2 CPU clock cycles for f
Symbol
1. If the device is clocked by the Internal Oscillator, it is no need to connect a clock source to the
2. V
MOSI
MISO
SCK
XTAL1 pin
CC
- 0.3 <
AV
CC
< V
Pins
PB4
PB3
PB5
ck
CC
ck
MOSI
MISO
SCK
<12MHz, 3 CPU clock cycles for f
<12MHz, 3 CPU clock cycles for f
+ 0.3, however,
PB3
PB4
PB5
XTAL1
RESET
GND
I/O
(1)
O
I
I
AV
CC
AVCC
Description
Serial data in
Serial data out
Serial clock
VCC
should always be within 2.7V - 5.5V
+2.7V - 5.5V
+2.7V - 5.5V
Table
(2)
ck
ck
96, the pin mapping for SPI
>=12MHz
>=12MHz
2486Z–AVR–02/11