AT91M42800A-33AI Atmel, AT91M42800A-33AI Datasheet
AT91M42800A-33AI
Specifications of AT91M42800A-33AI
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AT91M42800A-33AI Summary of contents
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... Available in a 144-lead LQFP Package (Green) and a 144-ball BGA Package (RoHS- compliant) 1. Description The AT91M42800A is a member of the Atmel AT91 16/32-bit microcontroller family, which is based on the ARM7TDMI processor core. This processor has a high-perfor- mance 32-bit RISC architecture with a high-density 16-bit instruction set and very low power consumption ...
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... Atmel’s high-density CMOS technology. By combining the ARM7TDMI processor core with on- chip SRAM and a wide range of peripheral functions including timers, serial communication con- trollers and a versatile clock generator on a monolithic chip, the AT91M42800A provides a highly-flexible and cost-effective solution to many compute-intensive applications. ...
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... Figure 2-2. 1779ES–ATARM–14-Apr-06 Pin Configuration in BGA144 Package (Top View AT91M42800A ...
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... Table 2-1. AT91M42800A Pinout in LQFP 144 Package Pin# Name Pin# 1 GND 37 2 GND 38 3 NLB/ VDDIO 48 13 GND A10 51 16 A11 52 17 A12 53 18 A13 54 19 A14 55 20 A15 56 21 A16 57 22 A17 58 23 A18 59 24 VDDIO 60 25 GND 61 26 A19 ...
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... Table 2-2. AT91M42800A Pinout in BGA 144 Package Pin# Name A1 PB1/NCS3 A2 NCS0 A3 NCS1 A4 GND A5 PLLRCB A6 GND A7 PLLRCA A8 GND A9 XOUT A10 XIN A11 MODE0 A12 PA22/NPCSB1 B1 NUB/NWR1 B2 PB0/NCS2 B3 VDDCORE B4 NWE/NWR0 B5 VDDPLL B6 TDO B7 VDDPLL B8 NWDOVF B9 PA26 B10 PA19/MISOB B11 PA24/NPCSB3 B12 PA23/NPCSB2 C1 NLB/ VDDIO ...
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... Pin Description Table 3-1. AT91M42800A Pin Description Module Name A0 - A23 D0 - D15 CS4 - CS7 NCS0 - NCS3 NWR0 NWR1 NRD EBI NWE NOE NUB NLB NWAIT BMS PME IRQ0 - IRQ3 AIC FIQ TCLK0 - TCLK5 TC TIOA0 - TIOA5 TIOB0 - TIOB5 SCK0 - SCK1 USART TXD0 - TXD1 ...
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... Table 3-1. AT91M42800A Pin Description (Continued) Module Name XIN XOUT CLOCK PLLRCA PLLRCB MCKO NRST Test and Reset MODE0 - MODE1 TMS TDI JTAG/ICE TDO TCK NTRST Emulation NTRI VDDIO VDDCORE Power VDDPLL GND 1779ES–ATARM–14-Apr-06 Function Oscillator Input or External Clock ...
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... PA9/TXD1/NTRI PA10/RXD1 P I PA11/SPCKA O PA12/MISOA PA13/MOSIA PA14/NPCSA0/NSSA PA15/NPCSA1 PA16/NPCSA2 PA17/NPCSA3 PA18/SPCKB PA19/MISOB PA20/MOSIB PA21/NPCSB0/NSSB PA22/NPCSB1 PA23/NPCSB2 PA24/NPCSB3 AT91M42800A 8 Embedded ICE ARM7TDMI Core ASB Internal RAM 8K Bytes ASB Controller AMBA™ Bridge AIC: Advanced Interrupt Controller 2 PDC USART0 Channels APB 2 PDC USART1 ...
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... Memories The AT91M42800A microcontroller embeds bytes of internal SRAM. The internal mem- ory is directly connected to the 32-bit data bus and is single-cycle accessible. This provides maximum performance of 30 MIPS at 33 MHz by using the ARM instruction set of the processor. The on-chip memory significantly reduces the system power consumption and improves its per- formance over external memory solutions ...
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... Peripheral operations Peripheral user interfaces DC characteristics AT91M42800A Power consumption Thermal and reliability considerations AC characteristics Product overview Ordering information Packaging information Soldering profile AT91M42800A 10 Document Title ARM7TDMI (Thumb) Datasheet AT91M42800A Datasheet AT91M42800A Electrical Characteristics AT91M42800A Summary Datasheet (this document) 1779ES–ATARM–14-Apr-06 ...
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... VDDPLL 7.2 Input/Output Considerations After the reset, the peripheral I/Os are initialized as inputs to provide the user with maximum flexibility recommended that in any application phase, the inputs to the AT91M42800A microcontroller be held at valid logic levels to minimize the power consumption. 7.3 Operating Modes The AT91M42800A has two pins dedicated to defining MODE0 and MODE1 operating modes. ...
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... Except for the program counter, the ARM core registers do not have defined reset states. When reset is active, the inputs of the AT91M42800A must be held at valid logic levels. The EBI address lines drive low during reset. All the peripheral clocks are disabled during reset to save power ...
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... Emulation Functions 7.6.1 Tri-state Mode The AT91M42800A provides a Tri-state mode, which is used for debug purposes in order to connect an emulator probe to an application board. In Tri-state mode the AT91M42800A contin- ues to function, but all the output pin drivers are tri-stated. To enter Tri-state mode, the pin NTRI must be held low during the last 10 SLCK clock cycles before the rising edge of NRST ...
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... Internal Memories The AT91M42800A microcontroller integrates an 8-Kbyte primary internal SRAM. All internal memories are 32 bits wide and single-clock cycle accessible. Byte (8-bit), half-word (16-bit) or word (32-bit) accesses are supported and are executed within one cycle. Fetching Thumb or ARM instructions is supported and internal memory can store twice as many Thumb instructions as ARM ones ...
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... The ARM vectors (Reset, Abort, Data Abort, Prefetch Abort, Undefined Instruction, Interrupt, Fast Interrupt) are mapped from address 0x0 to address 0x20. In order to allow these vectors to be redefined dynamically by the software, the AT91M42800A microcontroller uses a remap command that enables switching between the boot memory and the internal SRAM bank addresses ...
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... Peripherals The AT91M42800A peripherals are connected to the 32-bit wide Advanced Peripheral Bus. Peripheral registers are only word accessible. Byte and half-word accesses are not supported byte or a half-word access is attempted, the memory controller automatically masks the lowest address bits and generates a word access ...
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... Peripheral Data Controller The AT91M42800A has an 8-channel PDC dedicated to the two on-chip USARTs and to the two on-chip SPIs. One PDC channel is connected to the receiving channel and one to the transmit- ting channel of each peripheral. The user interface of a PDC channel is integrated in the memory space of each USART channel and in the memory space of each SPI ...
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... PIO: Parallel I/O Controller The AT91M42800A has 54 programmable I/O lines. I/O lines are multiplexed with an external signal of a peripheral to optimize the use of available package pins. These lines are controlled by two separate and identical PIO Controllers called PIOA and PIOB. Each PIO controller also provides an internal interrupt signal to the Advanced Interrupt Controller and insertion of a sim- ple input glitch filter on any of the PIO pins ...
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... SPI: Serial Peripheral Interface The AT91M42800A includes two SPIs that provide communication with external devices in Mas- ter or Slave mode. They are independent, and are referred to by the letters A and B. Each SPI has four external chip selects that can be connected devices. The data length is pro- grammable from 8- to 16-bit. 1779ES– ...
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... Packaging Information Figure 9-1. 144-lead LQFP Package Drawing AT91M42800A 20 1779ES–ATARM–14-Apr-06 ...
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... Min 0.09 0.09 0.45 0.08 0.08 0 0.05 1.35 Tolerances and form of position b Min Nom Max Min 0.17 0.22 0.27 0.17 mg AT91M42800A Nom Max 0.2 0.16 0.6 0.75 1.00 REF 0.2 3 1.6 0.15 1.4 1.45 0.2 0.2 b1 Nom Max e BSC ccc ...
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... Figure 9-2. 144-ball Ball Grid Array Package Drawing Table 9-4. Device and 144-ball BGA Package Maximum Weight 584 AT91M42800A 22 TOP VIEW SIDE VIEW mg BOTTOM VIEW Max. Symbol 1779ES–ATARM–14-Apr-06 ...
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... The package is certified to be backward compatible with Pb/Sn soldering profile. gives the recommended soldering profile from J-STD-20C. Soldering Profile RoHS Compliant Package It is recomended to apply a soldering temperature higher than 250°C. AT91M42800A Green Package 3 C/sec. max. 180 sec. max. 60 sec. to 150 sec. ...
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... Ordering Information Table 11-1. Ordering Information Ordering Code AT91M42800A-33CJ AT91M42800A-33AU AT91M42800A 24 Package Package Type BGA 144 RoHS-compliant LQFP 144 Green Operating Temperature Range Industrial (- 1779ES–ATARM–14-Apr-06 ...
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... Section 7.5.2 ”NTRST Pin” on page Updated Section 10. ”Soldering Profile” on page 23 1779ES remove leaded package references. 1779ES–ATARM–14-Apr-06 and “Soldering Profile” on page 23 with new data on 12. and Section 11. ”Ordering Information” on page 24 AT91M42800A Change Request Ref. 05-329 05-474 to 25 ...
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... AT91M42800A 26 1779ES–ATARM–14-Apr-06 ...
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... Disclaimer: The information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise, to any intellectual property right is granted by this document or in connection with the sale of Atmel products. EXCEPT AS SET FORTH IN ATMEL’S TERMS AND CONDI- TIONS OF SALE LOCATED ON ATMEL’S WEB SITE, ATMEL ASSUMES NO LIABILITY WHATSOEVER AND DISCLAIMS ANY EXPRESS, IMPLIED OR STATUTORY WARRANTY RELATING TO ITS PRODUCTS INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT ...