at91m42800 ATMEL Corporation, at91m42800 Datasheet
at91m42800
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at91m42800 Summary of contents
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... The AT91M42800 is manufactured using Atmel’s high-density CMOS technology. By combining the ARM7TDMI processor core with on-chip SRAM and a wide range of peripheral functions including timers, serial communication controllers and a versatile clock generator on a monolithic chip, the AT91M42800 provides a highly flexible and cost-effective solution to many compute-intensive applications. AT91 ® ...
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... Pin Configuration Figure 1. Pin Configuration in TQFP144 Package (Top View) Figure 2. Pin Configuration in BGA144 Package (Top View AT91M42800 2 108 73 109 AT91M42800 33AI 144 ...
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... Table 1. AT91M42800 Pinout in TQFP 144 Package Pin AT91M42800 Pin 1 GND 2 GND 3 NLB/ VDDIO 13 GND A10 16 A11 17 A12 18 A13 19 A14 20 A15 21 A16 22 A17 23 A18 24 VDDIO 25 GND 26 A19 27 PB2/A20/CS7 28 PB3/A21/CS6 29 PB4/A22/CS5 30 PB5/A23/CS4 ...
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... Table 2. AT91M42800 Pinout in BGA 144 Package Pin AT91M42800 A1 PB1/NCS3 A2 NCS0 A3 NCS1 A4 GND A5 PLLRCB A6 GND A7 PLLRCA A8 GNDPLL A9 XOUT A10 XIN A11 GND A12 PA22/NPCSB1 B1 NUB/NWR1 B2 PB0/NCS2 B3 VDDCORE B4 NWE/NWR0 B5 VDDPLL B6 TDO B7 VDDPLL B8 NWDOVF B9 PA26 B10 PA19/MISOB B11 PA24/NPCSB3 B12 PA23/NPCSB2 C1 NLB/ VDDIO ...
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... Pin Description Table 3. AT91M42800 Pin Description Module Name A0 - A23 D0 - D15 CS4 - CS7 NCS0 - NCS3 NWR0 NWR1 NRD EBI NWE NOE NUB NLB NWAIT HOLD HOLDA BMS IRQ0 - IRQ3 AIC FIQ TCLK0 - TCLK5 TC TIOA0 - TIOA5 TIOB0 - TIOB5 SCK0 - SCK1 USART TXD0 - TXD1 ...
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... Table 3. AT91M42800 Pin Description (Continued) Module Name JTAGSEL JTAG/ICE TMS TDI TDO TCK NTRST Emulation NTRI VDDIO VDDCORE Power VDDPLL GND AT91M42800 6 Function JTAG/ ICE selection Test Mode Select Test Data In Test Data Out Test Clock Test Reset Input Tri-state Mode Enable ...
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... Block Diagram Figure 3. AT91M42800 JTAGSEL NTRST TMS TDO TDI TCK XIN XOUT PLLRCA PLLRCB PA25/MCKO PA26 PA0/IRQ0 PA1/IRQ1 PA2/IRQ2 PA3/IRQ3 PA4/FIQ PA5/SCK0 PA6/TXD0 PA7/RXD0 PA8/SCK1 PA9/TXD1/NTRI PA10/RXD1 P I PA11/SPCKA O PA12/MISOA PA13/MOSIA PA14/NPCSA0/NSSA PA15/NPCSA1 PA16/NPCSA2 PA17/NPCSA3 PA18/SPCKB PA19/MISOB PA20/MOSIB PA21/NPCSB0/NSSB PA22/NPCSB1 PA23/NPCSB2 ...
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... ARM7TDMI processor on dedicated pins, offering a complete, low-cost and easy-to-use debug solution for tar- get debugging. Memories The AT91M42800 Microcontroller embeds bytes of internal SRAM. The internal memory is directly con- nected to the 32-bit data bus and is single-cycle accessible. This provides maximum performance of 30 MIPS at 33 MHz by using the ARM instruction set of the processor ...
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Supervisor Mode Protection The following system peripherals are protected against unintentional accesses by the Supervisor Operating Mode. • External Bus Interface (EBI) • Power Management Controller (PMC) • System Timers (ST) • Special Function (SF) 9 ...
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... Associated Documentation Information Internal architecture of processor ARM/Thumb instruction sets Embedded in-circuit emulator Mapping Peripheral operation Peripheral user interface Timings DC characteristics AT91M42800 10 Document Title ARM7TDMI (Thumb) Datasheet AT91M42800 Datasheet AT91M42800 Electrical Characteristics Datasheet ...
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... Except for the program counter the ARM core registers do not have defined reset states. When reset is active, the inputs of the AT91M42800 must be held at valid logic levels. The EBI address lines drive low during reset. All the peripheral clocks are disabled during reset to save power ...
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... Abort, Undefined Instruction, Interrupt, Fast Interrupt) are mapped from address 0x0 to address 0x20. In order to allow these vectors to be redefined dynamically by the soft- ware, the AT91M42800 Microcontroller uses a remap command that enables switching between the boot mem- ory and the internal RAM bank addresses. The remap command is accessible through the EBI User Interface, by writing one in RCB of EBI_RCR (Remap Control Register) ...
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... This eliminates the need for interrupt masking at the AIC or Core level in real-time and multi-tasking systems. Peripheral Data Controller The AT91M42800 has an 8-channel PDC dedicated to the two on-chip USARTs and to the two on-chip SPIs. One PDC channel is connected to the receiving channel and one to the transmitting channel of each peripheral ...
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... External sources can be programmed to be positive or negative edge triggered or high or low level sensitive. PIO: Parallel I/O Controller The AT91M42800 has 54 programmable I/O lines. I/O lines are multiplexed with an external signal of a peripheral to optimize the use of available package pins. These lines are controlled by two separate and identical PIO Controllers called PIOA and PIOB ...
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... Each Timer/Counter block operates independently and has a complete set of block and channel registers. SPI: Serial Peripheral Interface The AT91M42800 includes two SPIs that provide commu- nication with external devices in master or slave mode. They are independent, and are referred to by the letters A and B ...
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... Ordering Information Max Speed Core Operating (MHz) Power Supply Range 33 2.7V to 3.6V 33 2.7V to 3.6V AT91M42800 16 RAM Ordering Code (Bytes) AT91M42800-33CI 8K AT91M42800-33AI Operating Package Temperature Range BGA 144 -40°C to 85°C TQFP 144 ...
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Package Outline 144-lead TQFP Table 5. Common Dimensions (mm) Symbol Min c 0.09 c1 0.09 L 0.45 L1 1.00 REF R2 0.08 R1 0.08 S 0.2 q 0° q1 0° q2 11° q3 11° 0.05 A2 1.35 Tolerances ...
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... Figure 4. 144-lead TQFP Package Drawing θ2 θ3 AT91M42800 18 θ θ ...
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Package Outline 144-ball BGA Figure 5. 144-ball BGA Package Drawing TOP VIEW SIDE VIEW BOTTOM VIEW Max. Symbol 19 ...
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... Atmel Corporation 2000. Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company’s standard war- ranty which is detailed in Atmel’s Terms and Conditions located on the Company’s web site. The Company assumes no responsibility for any errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without notice, and does not make any commitment to update the information contained herein ...