AT91M42800A-33AI Atmel, AT91M42800A-33AI Datasheet - Page 15

• Manufacturer Part Number: AT91M42800A-33AI
• Description: IC ARM7 MCU 144 TQFP
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91M42800A-33AI

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 33MHz
• Connectivity: EBI/EMI, SPI, UART/USART
• Peripherals: WDT
• Number Of I /o: 54
• Program Memory Type: ROMless
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• For Use With: AT91EB42 - KIT EVAL FOR ARM AT91M42800A
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

7.7.4
7.7.5
7.7.6
1779ES–ATARM–14-Apr-06
Remap Command
Abort Control
External Bus Interface
The pin BMS is multiplexed with the I/O line PA27 that can be programmed after reset like any
standard PIO line.
Table 7-1.
The ARM vectors (Reset, Abort, Data Abort, Prefetch Abort, Undefined Instruction, Interrupt,
Fast Interrupt) are mapped from address 0x0 to address 0x20. In order to allow these vectors to
be redefined dynamically by the software, the AT91M42800A microcontroller uses a remap
command that enables switching between the boot memory and the internal SRAM bank
addresses. The remap command is accessible through the EBI User Interface, by writing one in
RCB of EBI_RCR (Remap Control Register). Performing a remap command is mandatory if
access to the other external devices (connected to chip selects 1 to 7) is required. The remap
operation can only be changed back by an internal reset or an NRST assertion.
The abort signal providing a Data Abort or a Prefetch Abort exception to the ARM7TDMI is
asserted in the following cases:
No abort is generated when reading the internal memory or by accessing the internal peripher-
als, whether the address is defined or not.
When the processor performs a forbidden write access in a mode-protected peripheral register,
the write is cancelled but no abort is generated.
The processor can perform word or half-word data access with a misaligned address when a
register relative load/store instruction is executed and the register contains a misaligned
address. In this case, whether the access is in write or in read, an abort is generated but the
access is not cancelled.
The Abort Status Register traces the source that caused the last abort. The address and the
type of abort are stored in registers of the External Bus Interface.
The External Bus Interface handles the accesses between addresses 0x0040 0000 and 0xFFC0
0000. It generates the signals that control access to the external devices, and can be configured
from eight 1-Mbyte banks up to four 16-Mbyte banks. In all cases it supports byte, half-word and
word aligned accesses.
For each of these banks, the user can program:
• When accessing an undefined address in the EBI address space
• When the ARM7TDMI performs a misaligned access
• Number of wait states
• Number of data float times (wait time after the access is finished to prevent any bus
• Data bus width (8-bit or 16-bit)
contention in case the device takes too long in releasing the bus)
BMS
1
0
Boot Mode Select
Boot Memory
External 8-bit memory NCS0
External 16-bit memory on NCS0
AT91M42800A
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