Manufacturer Part NumberATMEGA8515-16AI
DescriptionIC AVR MCU 8K 16MHZ IND 44-TQFP
SeriesAVR® ATmega
ATMEGA8515-16AI datasheets

Specifications of ATMEGA8515-16AI

Core ProcessorAVRCore Size8-Bit
Speed16MHzConnectivityEBI/EMI, SPI, UART/USART
PeripheralsBrown-out Detect/Reset, POR, PWM, WDTNumber Of I /o35
Program Memory Size8KB (4K x 16)Program Memory TypeFLASH
Eeprom Size512 x 8Ram Size512 x 8
Voltage - Supply (vcc/vdd)4.5 V ~ 5.5 VOscillator TypeInternal
Operating Temperature-40°C ~ 85°CPackage / Case44-TQFP, 44-VQFP
Lead Free Status / RoHS StatusContains lead / RoHS non-compliantData Converters-
Page 1
Page 2
Page 3
Page 4
Page 5
Page 6
Page 7
Page 8
Page 9
Page 10
Page 1/257

Download datasheet (2Mb)Embed
High-performance, Low-power AVR
RISC Architecture
– 130 Powerful Instructions – Most Single Clock Cycle Execution
– 32 x 8 General Purpose Working Registers
– Fully Static Operation
– Up to 16 MIPS Throughput at 16 MHz
– On-chip 2-cycle Multiplier
Nonvolatile Program and Data Memories
– 8K Bytes of In-System Self-programmable Flash
Endurance: 10,000 Write/Erase Cycles
– Optional Boot Code Section with Independent Lock bits
In-System Programming by On-chip Boot Program
True Read-While-Write Operation
– 512 Bytes EEPROM
Endurance: 100,000 Write/Erase Cycles
– 512 Bytes Internal SRAM
– Up to 64K Bytes Optional External Memory Space
– Programming Lock for Software Security
Peripheral Features
– One 8-bit Timer/Counter with Separate Prescaler and Compare Mode
– One 16-bit Timer/Counter with Separate Prescaler, Compare Mode, and Capture
– Three PWM Channels
– Programmable Serial USART
– Master/Slave SPI Serial Interface
– Programmable Watchdog Timer with Separate On-chip Oscillator
– On-chip Analog Comparator
Special Microcontroller Features
– Power-on Reset and Programmable Brown-out Detection
– Internal Calibrated RC Oscillator
– External and Internal Interrupt Sources
– Three Sleep Modes: Idle, Power-down and Standby
I/O and Packages
– 35 Programmable I/O Lines
– 40-pin PDIP, 44-lead TQFP, 44-lead PLCC, and 44-pad QFN/MLF
Operating Voltages
– 2.7 - 5.5V for ATmega8515L
– 4.5 - 5.5V for ATmega8515
Speed Grades
– 0 - 8 MHz for ATmega8515L
– 0 - 16 MHz for ATmega8515
8-bit Microcontroller
with 8K Bytes

ATMEGA8515-16AI Summary of contents

  • Page 1

    ... PDIP, 44-lead TQFP, 44-lead PLCC, and 44-pad QFN/MLF • Operating Voltages – 2.7 - 5.5V for ATmega8515L – 4.5 - 5.5V for ATmega8515 • Speed Grades – MHz for ATmega8515L – MHz for ATmega8515 ® 8-bit Microcontroller 8-bit Microcontroller with 8K Bytes In-System Programmable ...

  • Page 2

    ... Pin Configurations Figure 1. Pinout ATmega8515 TQFP/MLF (MOSI) PB5 1 (MISO) PB6 2 (SCK) PB7 3 RESET 4 (RXD) PD0 5 NC* 6 (TXD) PD1 7 (INT0) PD2 8 (INT1) PD3 9 (XCK) PD4 10 (OC1A) PD5 11 ATmega8515(L) 2 PDIP (OC0/T0) PB0 1 40 VCC (T1) PB1 2 39 PA0 (AD0) (AIN0) PB2 3 38 PA1 (AD1) ...

  • Page 3

    ... Overview Block Diagram 2512K–AVR–01/10 The ATmega8515 is a low-power CMOS 8-bit microcontroller based on the AVR enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the ATmega8515 achieves throughputs approaching 1 MIPS per MHz allowing the sys- tem designer to optimize power consumption versus processing speed. ...

  • Page 4

    ... In-System Self-programmable Flash on a monolithic chip, the Atmel ATmega8515 is a powerful microcontroller that provides a highly flexible and cost effective solution to many embedded control applications. The ATmega8515 is supported with a full suite of program and system development tools including: C Compilers, Macro assemblers, Program debugger/simulators, In-cir- cuit Emulators, and Evaluation kits. ...

  • Page 5

    ... The Port E pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port E also serves the functions of various special features of the ATmega8515 as listed on page 74. Reset input. A low level on this pin for longer than the minimum pulse length will gener- ate a reset, even if the clock is not running ...

  • Page 6

    ... Resources ATmega8515( comprehensive set of development tools, application notes and datasheets are avail- able for download on http://www.atmel.com/avr. 2512K–AVR–01/10 ...

  • Page 7

    ... These code examples assume that the part specific header file is included before compilation. Be aware that not all C Compiler vendors include bit defini- tions in the header files and interrupt handling compiler dependent. Please confirm with the C Compiler documentation for more details. ATmega8515(L) 7 ...

  • Page 8

    ... AVR CPU Core Introduction Architectural Overview ATmega8515(L) 8 This section discusses the AVR core architecture in general. The main function of the CPU core is to ensure correct program execution. The CPU must therefore be able to access memories, perform calculations, control peripherals, and handle interrupts. Figure 3. Block Diagram of the AVR Architecture ...

  • Page 9

    ... The ALU operations are divided into three main categories – arithmetic, logical, and bit-func- tions. Some implementations of the architecture also provide a powerful multiplier supporting both signed/unsigned multiplication and fractional format. See the “Instruc- tion Set” section for a detailed description. ATmega8515(L) 9 ...

  • Page 10

    ... Status Register ATmega8515(L) 10 The Status Register contains information about the result of the most recently executed arithmetic instruction. This information can be used for altering program flow in order to perform conditional operations. Note that the Status Register is updated after all ALU operations, as specified in the Instruction Set Reference. This will in many cases remove the need for using the dedicated compare instructions, resulting in faster and more compact code ...

  • Page 11

    ... Data Space. Although not being phys- ically implemented as SRAM locations, this memory organization provides great flexibility in access of the registers, as the X-, Y-, and Z-pointer Registers can be set to index any register in the file. ATmega8515(L) 0 Addr. R0 ...

  • Page 12

    ... The X-register, Y-register, and Z-register Stack Pointer ATmega8515(L) 12 The registers R26..R31 have some added functions to their general purpose usage. These registers are 16-bit address pointers for indirect addressing of the Data Space. The three indirect address registers X, Y, and Z are defined as described in Figure 5. ...

  • Page 13

    ... INT0 – the External Interrupt Request 0. The Interrupt Vectors can be moved to the start of the Boot Flash section by setting the IVSEL bit in the General Interrupt Control Regis- ter (GICR). Refer to “Interrupts” on page 54 for more information. The Reset Vector can ATmega8515(L) , directly generated from the selected clock CPU ...

  • Page 14

    ... ATmega8515(L) 14 also be moved to the start of the Boot Flash section by programming the BOOTRST Fuse, see “Boot Loader Support – Read-While-Write Self-Programming” on page 166. When an interrupt occurs, the Global Interrupt Enable I-bit is cleared and all interrupts are disabled. The user software can write logic one to the I-bit to enable nested inter- rupts. All enabled interrupts can then interrupt the current interrupt routine. The I-bit is automatically set when a Return from Interrupt instruction – ...

  • Page 15

    ... This increase comes in addition to the start-up time from the selected sleep mode. A return from an interrupt handling routine takes four clock cycles. During these four clock cycles, the Program Counter (two bytes) is popped back from the Stack, the Stack Pointer is incremented by two, and the I-bit in SREG is set. ATmega8515(L) 15 ...

  • Page 16

    ... Boot Program section and Application Program section. The Flash memory has an endurance of at least 10,000 write/erase cycles. The ATmega8515 Program Counter (PC bits wide, thus addressing the 4K Program memory locations. The operation of Boot Program section and associated Boot Lock bits for software protection are described in detail in “ ...

  • Page 17

    ... SRAM. The first 96 locations address the Register File and I/O Mem- ory, and the next 512 locations address the internal data SRAM. An optional external data SRAM can be used with the ATmega8515. This SRAM will occupy an area in the remaining address locations in the 64K address space. This area starts at the address following the internal SRAM ...

  • Page 18

    ... Data Memory Access Times ATmega8515(L) 18 Figure 9. Data Memory Map Data Memory 32 Registers 64 I/O Registers Internal SRAM (512 x 8) External SRAM (0 - 64K x 8) This section describes the general access timing concepts for internal memory access. The internal data SRAM access is performed in two clk 10 ...

  • Page 19

    ... Register – EEARH and EEARL 2512K–AVR–01/10 The ATmega8515 contains 512 bytes of data EEPROM memory organized as a separate data space, in which single bytes can be read and written. The EEPROM has an endurance of at least 100,000 write/erase cycles. The access between the EEPROM and the CPU is described in the following, specifying the EEPROM Address Registers, the EEPROM Data Register, and the EEPROM Control Register ...

  • Page 20

    ... Bits 7..4 – Res: Reserved Bits These bits are reserved bits in the ATmega8515 and will always read as zero. • Bit 3 – EERIE: EEPROM Ready Interrupt Enable Writing EERIE to one enables the EEPROM Ready Interrupt if the I-bit in SREG is set. Writing EERIE to zero disables the interrupt. The EEPROM Ready interrupt generates a constant interrupt when EEWE is cleared. • ...

  • Page 21

    ... The examples also assume that no Flash Boot Loader is present in the software. If such code is present, the EEPROM write function must also wait for any ongoing SPM com- mand to finish. ATmega8515(L) (1) Oscillator Cycles Typ Programming Time 8448 8 ...

  • Page 22

    ... ATmega8515(L) 22 Assembly Code Example EEPROM_write: ; Wait for completion of previous write sbic EECR,EEWE rjmp EEPROM_write ; Set up address (r18:r17) in address register out EEARH, r18 out EEARL, r17 ; Write data (r16) to data register out EEDR,r16 ; Write logical one to EEMWE sbi EECR,EEMWE ; Start eeprom write by setting EEWE ...

  • Page 23

    ... EEPROM write operation will continue, and will complete before the Write Access time has passed. However, when the write operation is completed, the crystal Oscillator continues running, and as a consequence, the device does not enter Power-down entirely therefore recommended to verify that the EEPROM write operation is com- pleted before entering Power-down. ATmega8515(L) 23 ...

  • Page 24

    ... The I/O space definition of the ATmega8515 is shown in “Register Summary” on page 239. All ATmega8515 I/Os and peripherals are placed in the I/O space. The I/O locations are accessed by the IN and OUT instructions, transferring data between the 32 general pur- pose working registers and the I/O space. I/O Registers within the address range $00 - $1F are directly bit-accessible using the SBI and CBI instructions ...

  • Page 25

    ... AD7:0: Multiplexed low-order address bus and data bus • A15:8: High-order address bus (configurable number of bits) • ALE: Address latch enable • RD: Read strobe • WR: Write strobe ATmega8515(L) 0x0000 Internal Memory 0x25F 0x260 Lower Sector SRW01 SRW00 SRL[2..0] Upper Sector ...

  • Page 26

    ... Address Latch Requirements ATmega8515(L) 26 The control bits for the External Memory Interface are located in three registers, the MCU Control Register – MCUCR, the Extended MCU Control Register – EMCUCR, and the Special Function IO Register – SFIOR. When the XMEM interface is enabled, it will override the settings in the data direction registers corresponding to the ports dedicated to the interface. For details about this port override, see the alternate functions in section “ ...

  • Page 27

    ... The most important parameters are the access time for the external memory in conjunction with the set-up requirement of the ATmega8515. The access time for the external memory is defined to be the time from receiving the chip select/address until the data of this address actually is driven on the bus ...

  • Page 28

    ... ATmega8515(L) 28 Figure 14. External Data Memory Cycles with SRWn1 = 0 and SRWn0 = 1 T1 System Clock (CLK ) CPU ALE A15:8 Prev. Addr. DA7:0 Prev. Data Address WR DA7:0 (XMBK = 0) Prev. Data Address DA7:0 (XMBK = 1) Prev. Data RD Note: 1. SRWn1 = SRW11 (upper sector) or SRW01 (lower sector), SRWn0 = SRW10 (upper ...

  • Page 29

    ... The SRL2, SRL1, and SRL0 bits select the splitting of these sectors, see Table 2 and Figure 11. By default, the SRL2, SRL1, and SRL0 bits are set to zero and the entire External Memory address space is treated as one sector. When the entire ATmega8515( ...

  • Page 30

    ... ATmega8515(L) 30 SRAM address space is configured as one sector, the wait states are configured by the SRW11 and SRW10 bits. Table 2. Sector Limits with Different Settings of SRL2..0 SRL2 SRL1 SRL0 • Bit 1 and Bit 6 MCUCR – SRW11, SRW10: Wait State Select Bits for Upper ...

  • Page 31

    ... Addressing above address 0x825F is not recommended, since this will address an external memory loca- tion that is already accessed by another (lower) address. To the Application software, the external 32 KB memory will appear as one linear 32 KB address space from 0x0260 to 0x825F. This is illustrated in Figure 17. ATmega8515( ...

  • Page 32

    ... ATmega8515(L) 32 Figure 17. Address Map with 32 KB External Memory Memory Configuration AVR Memory Map 0x0000 Internal Memory 0x025F 0x0260 External 0x7FFF 0x8000 Memory 0x825F 0x8260 (Unused) 0xFFFF External 32K SRAM 0x0000 0x025F 0x0260 0x7FFF 2512K–AVR–01/10 ...

  • Page 33

    ... OFFSET 0x2000 void XRAM_example(void) { unsigned char *p = (unsigned char *) (OFFSET + 1); DDRC = 0xFF; PORTC = 0x00; SFIOR = (1<<XMM1) | (1<<XMM0 0xaa; SFIOR = 0x00 0x55; } Note: 1. See “About Code Examples” on page 7. Care must be exercised using this option as most of the memory is masked away. ATmega8515(L) 33 ...

  • Page 34

    ... CPU Clock – clk CPU I/O Clock – clk I/O ATmega8515(L) 34 Figure 18 presents the principal clock systems in the AVR and their distribution. All of the clocks need not be active at a given time. In order to reduce power consumption, the clocks to modules not being used can be halted by using different sleep modes, as described in “ ...

  • Page 35

    ... The Watchdog Oscillator is used for timing this real-time part of the start-up time. The number of WDT Oscillator cycles used for each time-out is shown in Table 6. The frequency of the Watchdog Oscil- lator is voltage dependent as shown in “ATmega8515 Typical Characteristics” on page 207. Table 6. Number of Watchdog Oscillator Cycles Typ Time-out ( ...

  • Page 36

    ... ATmega8515( use, the amount of stray capacitance, and the electromagnetic noise of the environ- ment. Some initial guidelines for choosing capacitors for use with crystals are given in Table 7. For ceramic resonators, the capacitor values given by the manufacturer should be used. Figure 19. Crystal Oscillator Connections The Oscillator can operate in three different modes, each optimized for a specific fre- quency range ...

  • Page 37

    ... SUT1..0 from Power-down ( ( 32K CK 11 Note: 1. These options should only be used if frequency stability at start-up is not important for the application. ATmega8515(L) Additional Delay from Recommended Reset (V = 5.0V) Usage CC – Crystal Oscillator, BOD enabled 4.1 ms Crystal Oscillator, fast rising power 65 ms Crystal Oscillator, ...

  • Page 38

    ... External RC Oscillator ATmega8515(L) 38 For timing insensitive applications, the external RC configuration shown in Figure 20 can be used. The frequency is roughly estimated by the equation f = 1/(3RC). C should be at least 22 pF. By programming the CKOPT Fuse, the user can enable an internal 36 pF capacitor between XTAL1 and GND, thereby removing the need for an external capacitor ...

  • Page 39

    ... Flash or EEPROM. Then the value can be read by software and loaded into the OSCCAL Register. When OSCCAL is zero, the lowest available frequency is chosen. Writing non-zero values to this register ATmega8515(L) Nominal Frequency (MHz) 1.0 2.0 4 ...

  • Page 40

    ... External Clock ATmega8515(L) 40 will increase the frequency of the internal Oscillator. Writing $FF to the register gives the highest available frequency. The calibrated Oscillator is used to time EEPROM and Flash access. If EEPROM or Flash is written, do not calibrate to more than 10% above the nominal frequency. Otherwise, the EEPROM or Flash write may fail. Note that the Oscillator is intended for calibration to 1 ...

  • Page 41

    ... The contents of the Register File and SRAM are unaltered when the device wakes up from sleep Reset occurs during sleep mode, the MCU wakes up and executes from the Reset Vector. Figure 18 on page 34 presents the different clock systems in the ATmega8515, and their distribution. The figure is helpful in selecting an appropriate sleep mode. Bit ...

  • Page 42

    ... Extended MCU Control Register – EMCUCR Idle Mode Power-down Mode ATmega8515(L) 42 Bit SM0 SRL2 SRL1 Read/Write R/W R/W R/W Initial Value • Bits 7 – SM0: Sleep Mode Select Bit 0 The Sleep Mode Select bits select between the three available sleep modes as shown in Table 16 ...

  • Page 43

    ... If the Watchdog Timer is enabled, it will be enabled in all sleep modes, and hence, always consume power. In the deeper sleep modes, this will contribute significantly to the total current consumption. Refer to page 53 for details on how to configure the Watchdog Timer. ATmega8515(L) Oscillators Wake-up Sources INT2 Main Clock ...

  • Page 44

    ... Port Pins ATmega8515(L) 44 When entering a sleep mode, all port pins should be configured to use minimum power. The most important thing is to ensure that no pins drive resistive loads. In sleep modes where the I/O clock (clk ) is stopped, the input buffers of the device will be disabled. ...

  • Page 45

    ... The time-out period of the delay counter is defined by the user through the CKSEL Fuses. The different selections for the delay period are presented in “Clock Sources” on page 35. The ATmega8515 has four sources of reset: • Power-on Reset. The MCU is reset when the supply voltage is below the Power-on Reset threshold (V ) ...

  • Page 46

    ... V production test. This guarantees that a Brown-out Reset will occur before voltage where correct operation of the microcontroller is no longer guaranteed. The test is performed using BODLEVEL=1 for ATmega8515L and BODLEVEL=0 for ATmega8515. BODLEVEL=1 is not applicable for ATmega8515. DATA BUS ...

  • Page 47

    ... V CC Figure 23. MCU Start-up, RESET Tied POT RST RESET t TOUT TIME-OUT INTERNAL RESET Figure 24. MCU Start-up, RESET Extended Externally V POT V CC RESET TIME-OUT INTERNAL RESET ATmega8515(L) rise. The RESET signal is activated CC decreases below the detection level RST t TOUT is below the CC 47 ...

  • Page 48

    ... MCU after the Time-out period t Figure 25. External Reset During Operation CC ATmega8515 has an On-chip Brown-out Detection (BOD) circuit for monitoring the V level during operation by comparing fixed trigger level. The trigger level for the BOD can be selected by the fuse BODLEVEL to be 2.7V (BODLEVEL unprogrammed ...

  • Page 49

    ... To make use of the Reset Flags to identify a reset condition, the user should read and then reset the MCUCSR as early as possible in the program. If the register is cleared before another reset occurs, the source of the reset can be found by examining the Reset Flags. ATmega8515( – ...

  • Page 50

    ... Chip Reset occurs. Eight different clock cycle periods can be selected to determine the reset period. If the reset period expires without another Watchdog Reset, the ATmega8515 resets and executes from the Reset Vector. For tim- ing details on the Watchdog Reset, refer to page 49. ...

  • Page 51

    ... Bits 7..5 – Res: Reserved Bits These bits are reserved bits in the ATmega8515 and will always read as zero. • Bit 4 – WDCE: Watchdog Change Enable This bit must be set when the WDE bit is written to logic zero. Otherwise, the Watchdog will not be disabled ...

  • Page 52

    ... ATmega8515( the same operation, write a logic one to WDCE and WDE. A logic one must be written to WDE even though it is set to one before the disable operation starts. 2. Within the next four clock cycles, write a logic 0 to WDE. This disables the Watchdog. In safety level not possible to disable the Watchdog Timer, even with the algo- rithm described above. See “ ...

  • Page 53

    ... In the same operation, write a logical one to WDCE and WDE. Even though the WDE always is set, the WDE must be written to one to start the timed sequence. 2. Within the next four clock cycles, in the same operation, write the WDP bits as desired, but with the WDCE bit cleared. The value written to the WDE bit is irrelevant. ATmega8515(L) 53 ...

  • Page 54

    ... Interrupts Interrupt Vectors in ATmega8515 ATmega8515(L) 54 This section describes the specifics of the interrupt handling as performed in ATmega8515. For a general explanation of the AVR interrupt handling, refer to “Reset and Interrupt Handling” on page 13. Table 22. Reset and Interrupt Vectors Program (2) Vector No. Address Source (1) 1 $000 RESET ...

  • Page 55

    ... The Boot Reset Address is shown in Table 78 on page 177. For the BOOTRST Fuse “1” means unprogrammed while “0” means programmed. The most typical and general program setup for the Reset and Interrupt Vector Addresses in ATmega8515 is: Address Labels Code $000 ...

  • Page 56

    ... ATmega8515(L) 56 When the BOOTRST Fuse is unprogrammed, the Boot section size set to 2K bytes and the IVSEL bit in the GICR Register is set before any interrupts are enabled, the most typical and general program setup for the Reset and Interrupt Vector Addresses is: ...

  • Page 57

    ... Interrupt Vectors are placed in the Application section and Boot Lock bit BLB12 is pro- gramed, interrupts are disabled while executing from the Boot Loader section. Refer to the section “Boot Loader Support – Read-While-Write Self-Programming” on page 166 for details on Boot Lock bits. ATmega8515(L) ; Set Stack Pointer to top of RAM ; Enable interrupts xxx ...

  • Page 58

    ... ATmega8515(L) 58 • Bit 0 – IVCE: Interrupt Vector Change Enable The IVCE bit must be written to logic one to enable change of the IVSEL bit. IVCE is cleared by hardware four cycles after it is written or when IVSEL is written. Setting the IVCE bit will disable interrupts, as explained in the IVSEL description above. See Code Example below ...

  • Page 59

    ... Port Functions” on page 64. Refer to the individual module sections for a full description of the alternate functions. Note that enabling the alternate function of some of the port pins does not affect the use of the other pins in the port as general digital I/O. ATmega8515( Logic See Figure " ...

  • Page 60

    ... Ports as General Digital I/O Configuring the Pin ATmega8515(L) 60 The ports are bi-directional I/O ports with optional internal pull-ups. Figure 30 shows a functional description of one I/O-port pin, here generically called Pxn. (1) Figure 30. General Digital I/O Pxn PUD: PULLUP DISABLE SLEEP: SLEEP CONTROL clk ...

  • Page 61

    ... The latch is closed when the clock is low, and goes transparent when the clock is high, as indicated by the shaded region of the “SYNC LATCH” signal. The signal value is latched when the system clock goes low clocked into the PINxn Register at the suc- ceeding positive clock edge. As indicated by the two arrows t ATmega8515(L) I/O Pull-up Comment ...

  • Page 62

    ... ATmega8515(L) 62 signal transition on the pin will be delayed between ½ and 1½ system clock period depending upon the time of assertion. When reading back a software assigned pin value, a nop instruction must be inserted as indicated in Figure 32. The out instruction sets the “SYNC LATCH” signal at the positive edge of the clock ...

  • Page 63

    ... Rising Edge, Falling Edge, or Any Logic Change on Pin” while the external interrupt is not enabled, the corresponding External Interrupt Flag will be set when resuming from the above mentioned sleep modes, as the clamping in these sleep modes produces the requested logic change. ATmega8515(L) / ...

  • Page 64

    ... Unconnected pins Alternate Port Functions ATmega8515( some pins are unused recommended to ensure that these pins have a defined level. Even though most of the digital inputs are disabled in the deep sleep modes as described above, floating inputs should be avoided to reduce current consumption in all other modes where the digital inputs are enabled (Reset, Active mode and Idle mode). ...

  • Page 65

    ... The following subsections shortly describe the alternate functions for each port, and relate the overriding signals to the alternate function. Refer to the alternate function description for further details. ATmega8515(L) Description If this signal is set, the pull-up enable is controlled by the PUOV signal. If this signal is cleared, the pull-up is enabled when {DDxn, PORTxn, PUD} = 0b010 ...

  • Page 66

    ... Special Function IO Register – SFIOR Alternate Functions of Port A ATmega8515(L) 66 Bit – XMBK XMM2 Read/Write R/W R/W R/W Initial Value • Bit 2 – PUD: Pull-up Disable When this bit is written to one, the pull-ups in the I/O ports are disabled even if the DDxn and PORTxn Registers are configured to enable the pull-ups ({DDxn, PORTxn} = 0b01). ...

  • Page 67

    ... Master, this pin is configured as an input regardless of the setting of DDB6. When the SPI is enabled as a Slave, the data direction of this pin is controlled by DDB6. When the pin is forced by the SPI input, the pull-up can still be con- trolled by the PORTB6 bit. ATmega8515(L) PA1/AD1 PA0/AD0 SRE SRE ~(WR | ADA) • ...

  • Page 68

    ... ATmega8515(L) 68 • MOSI – Port B, Bit 5 MOSI: SPI Master Data output, Slave Data input for SPI channel. When the SPI is enabled as a Slave, this pin is configured as an input regardless of the setting of DDB5. When the SPI is enabled as a Master, the data direction of this pin is controlled by DDB5 ...

  • Page 69

    ... Table 31. Overriding Signals for Alternate Functions in PB3..PB0 Signal Name PB3/AIN1 PUOE 0 PUOV 0 DDOE 0 DDOV 1 PVOE 0 PVOV 0 DIEOE 0 DIEOV 0 DI – AIO AIN1 INPUT ATmega8515(L) PB5/MOSI SPE • MSTR PORTB5 • PUD SPE • MSTR 0 SPE • MSTR SPI MSTR OUTPUT 0 0 SPI SLAVE INPUT – PB2/AIN0 PB1/ ...

  • Page 70

    ... Alternate Functions of Port C ATmega8515(L) 70 The Port C pins with alternate functions are shown in Table 32. Table 32. Port C Pins Alternate Functions Port Pin Alternate Function PC7 A15 (External memory interface address bit 15) PC6 A14 (External memory interface address bit 14) PC5 A13 (External memory interface address bit 13) ...

  • Page 71

    ... PUOV 0 DDOE SRE • (XMM<5) DDOV 1 PVOE SRE • (XMM<5) PVOV A11 DIEOE 0 DIEOV 0 DI – AIO – ATmega8515(L) PC6/A14 PC5/A13 SRE • (XMM<2) SRE • (XMM< SRE • (XMM<2) SRE • (XMM< SRE • (XMM<2) SRE • (XMM<3) A14 A13 – ...

  • Page 72

    ... Alternate Functions of Port D ATmega8515(L) 72 The Port D pins with alternate functions are shown in Table 35. Table 35. Port D Pins Alternate Functions Port Pin Alternate Function PD7 RD (Read Strobe to External Memory) PD6 WR (Write Strobe to External Memory) PD5 OC1A (Timer/Counter1 Output Compare A Match Output) PD4 XCK (USART External Clock Input/Output) ...

  • Page 73


  • Page 74

    ... Alternate Functions of Port E ATmega8515(L) 74 The Port E pins with alternate functions are shown in Table 38. Table 38. Port E Pins Alternate Functions Port Pin Alternate Function PE2 OC1B (Timer/Counter1 Output Compare B Match Output) PE1 ALE (Address Latch Enable to External Memory) ICP (Timer/Counter1 Input Capture Pin) ...

  • Page 75

    ... R R Initial Value N/A N/A N/A Bit PORTC7 PORTC6 PORTC5 Read/Write R/W R/W R/W Initial Value Bit DDC7 DDC6 DDC5 Read/Write R/W R/W R/W Initial Value ATmega8515( PORTA4 PORTA3 PORTA2 PORTA1 R/W R/W R/W R DDA4 DDA3 DDA2 DDA1 R/W R/W R/W R ...

  • Page 76

    ... PINC Port D Data Register – PORTD Port D Data Direction Register – DDRD Port D Input Pins Address – PIND Port E Data Register – PORTE Port E Data Direction Register – DDRE Port E Input Pins Address – PINE ATmega8515(L) 76 Bit PINC7 PINC6 PINC5 Read/Write R ...

  • Page 77

    ... Any logical change on INT1 generates an interrupt request The falling edge of INT1 generates an interrupt request The rising edge of INT1 generates an interrupt request. • Bit 1, 0 – ISC01, ISC00: Interrupt Sense Control 0 Bit 1 and Bit 0 ATmega8515( SM1 ISC11 ISC10 ISC01 ISC00 R/W ...

  • Page 78

    ... Extended MCU Control Register – EMCUCR General Interrupt Control Register – GICR ATmega8515(L) 78 The External Interrupt 0 is activated by the external pin INT0 if the SREG I-flag and the corresponding interrupt mask are set. The level and edges on the external INT0 pin that activate the interrupt are defined in Table 41 ...

  • Page 79

    ... INT2 interrupt disabled, the input buffer on this pin will be disabled. This may cause a logic change in internal signals which will set the INTF2 Flag. See “Digital Input Enable and Sleep Modes” on page 63 for more information. ATmega8515( ...

  • Page 80

    ... Overflow and Compare Match Interrupt Sources (TOV0 and OCF0) A simplified block diagram of the 8-bit Timer/Counter is shown in Figure 34. For the actual placement of I/O pins, refer to “Pinout ATmega8515” on page 2. CPU accessible I/O Registers, including I/O bits and I/O pins, are shown in bold. The device-specific I/O Register and bit locations are listed in the “ ...

  • Page 81

    ... DATA BUS count clear TCNTn direction bottom Signal description (internal signals): count Increment or decrement TCNT0 by 1. direction Select between increment and decrement. clear Clear TCNT0 (set all bits to zero). ATmega8515(L) ). TOVn (Int.Req.) Clock Select Edge Detector clk Tn Control Logic ( From Prescaler ) top Tn ...

  • Page 82

    ... Output Compare Unit ATmega8515(L) 82 clk Timer/Counter clock, referred to as clk Tn top Signalize that TCNT0 has reached maximum value. bottom Signalize that TCNT0 has reached minimum value (zero). Depending of the mode of operation used, the counter is cleared, incremented, or dec- remented at each timer clock (clk T0 clock source, selected by the Clock Select bits (CS02:0) ...

  • Page 83

    ... Compare (FOC0) strobe bits in Normal mode. The OC0 Register keeps its value even when changing between Waveform Generation modes. Be aware that the COM01:0 bits are not double buffered together with the compare value. Changing the COM01:0 bits will take effect immediately. ATmega8515(L) 83 ...

  • Page 84

    ... Compare Match Output Unit Compare Output Mode and Waveform Generation ATmega8515(L) 84 The Compare Output mode (COM01:0) bits have two functions. The Waveform Genera- tor uses the COM01:0 bits for defining the Output Compare (OC0) state at the next Compare Match. Also, the COM01:0 bits control the OC0 pin output source. Figure 37 shows a simplified schematic of the logic affected by the COM01:0 bit setting ...

  • Page 85

    ... An interrupt can be generated each time the counter value reaches the TOP value by using the OCF0 Flag. If the interrupt is enabled, the interrupt handler routine can be used for updating the TOP value. However, changing TOP to a value close to BOTTOM ATmega8515(L) OCn Interrupt Flag Set 2 ...

  • Page 86

    ... Fast PWM Mode ATmega8515(L) 86 when the counter is running with none or a low prescaler value must be done with care since the CTC mode does not have the double buffering feature. If the new value written to OCR0 is lower than the current value of TCNT0, the counter will miss the Compare Match ...

  • Page 87

    ... This feature is similar to the OC0 toggle in CTC mode, except the double buffer feature of the output compare unit is enabled in the fast PWM mode. ATmega8515(L) OCRn Interrupt Flag Set OCRn Update and TOVn Interrupt Flag Set ...

  • Page 88

    ... Phase Correct PWM Mode ATmega8515(L) 88 The phase correct PWM mode (WGM01 provides a high resolution phase correct PWM waveform generation option. The phase correct PWM mode is based on a dual- slope operation. The counter counts repeatedly from BOTTOM to MAX and then from MAX to BOTTOM. In non-inverting Compare Output mode, the Output Compare (OC0) is cleared on the Compare Match between TCNT0 and OCR0 while upcounting, and set on the Compare Match while downcounting ...

  • Page 89

    ... The figure shows the count sequence close to the MAX value in all modes other than phase correct PWM mode. Figure 41. Timer/Counter Timing Diagram, no Prescaling clk I/O clk Tn (clk /1) I/O TCNTn MAX - 1 TOVn Figure 42 shows the same timing data, but with the prescaler enabled. ATmega8515(L) f clk_I/O = ----------------- - ⋅ N 510 T0 MAX BOTTOM ) is therefore BOTTOM + 1 89 ...

  • Page 90

    ... ATmega8515(L) 90 Figure 42. Timer/Counter Timing Diagram, with Prescaler (f clk I/O clk Tn (clk /8) I/O TCNTn MAX - 1 TOVn Figure 43 shows the setting of OCF0 in all modes except CTC mode. Figure 43. Timer/Counter Timing Diagram, Setting of OCF0, with Prescaler (f clk I/O clk Tn (clk /8) I/O TCNTn OCRn - 1 OCRn OCFn Figure 44 shows the setting of OCF0 and the clearing of TCNT0 in CTC mode ...

  • Page 91

    ... These bits control the Output Compare pin (OC0) behavior. If one or both of the COM01:0 bits are set, the OC0 output overrides the normal port functionality of the I/O pin it is connected to. However, note that the Data Direction Register (DDR) bit corre- sponding to the OC0 pin must be set in order to enable the output driver. ATmega8515( ...

  • Page 92

    ... ATmega8515(L) 92 When OC0 is connected to the pin, the function of the COM01:0 bits depends on the WGM01:0 bit setting. Table 45 shows the COM01:0 bit functionality when the WGM01:0 bits are set to a normal or CTC mode (non-PWM). Table 45. Compare Output Mode, non-PWM Mode COM01 COM00 ...

  • Page 93

    ... Timer/Counter0 Overflow interrupt is enabled. The corresponding interrupt is executed if an overflow in Timer/Counter0 occurs, i.e., when the TOV0 bit is set in the Timer/Coun- ter Interrupt Flag Register – TIFR. • Bit 0 – OCIE0: Timer/Counter0 Output Compare Match Interrupt Enable ATmega8515(L) /(No prescaling) /8 (From prescaler) /64 (From prescaler) ...

  • Page 94

    ... Timer/Counter Interrupt Flag Register – TIFR ATmega8515(L) 94 When the OCIE0 bit is written to one, and the I-bit in the Status Register is set (one), the Timer/Counter0 Compare Match interrupt is enabled. The corresponding interrupt is executed if a Compare Match in Timer/Counter0 occurs, i.e., when the OCF0 bit is set in the Timer/Counter Interrupt Flag Register – ...

  • Page 95

    ... Each half period of the external clock applied must be longer than one system clock cycle to ensure correct sampling. The external clock must be guaranteed to have less than half the system clock frequency (f ATmega8515(L) ). Alternatively, one of four taps from CLK_I/O /256 /1024. ...

  • Page 96

    ... Special Function IO Register – SFIOR ATmega8515(L) 96 the edge detector uses sampling, the maximum frequency of an external clock it can detect is half the sampling frequency (Nyquist sampling theorem). However, due to vari- ation of the system clock frequency and duty cycle caused by Oscillator source (crystal, ...

  • Page 97

    ... A simplified block diagram of the 16-bit Timer/Counter is shown in Figure 47. For the actual placement of I/O pins, refer to “Pin Configurations” on page 2. CPU accessible I/O Registers, including I/O bits and I/O pins, are shown in bold. The device-specific I/O Register and bit location are listed in the “16-bit Timer/Counter Register Description” on page 119. ATmega8515(L) 97 ...

  • Page 98

    ... Registers ATmega8515(L) 98 Figure 47. 16-bit Timer/Counter Block Diagram Count Clear Direction Timer/Counter TCNTn = OCRnA = OCRnB ICRn TCCRnA Note: 1. Refer to Figure 1 on page 2, Table 29 on page 67, and Table 35 on page 72 for Timer/Counter1 pin placement and description. The Timer/Counter (TCNT1), Output Compare Registers (OCR1A/B), and Input Capture Register (ICR1) are all 16-bit registers. Special procedures must be followed when accessing the 16-bit registers. These procedures are described in the section “ ...

  • Page 99

    ... PWM11 is changed to WGM11. • CTC1 is changed to WGM12. The following bits are added to the 16-bit Timer/Counter Control Registers: • FOC1A and FOC1B are added to TCCR1A. • WGM13 is added to TCCR1B. The 16-bit Timer/Counter has improvements that will affect the compatibility in some special cases. ATmega8515(L) 99 ...

  • Page 100

    ... Accessing 16-bit Registers ATmega8515(L) 100 The TCNT1, OCR1A/B, and ICR1 are 16-bit registers that can be accessed by the AVR CPU via the 8-bit data bus. The 16-bit register must be byte accessed using two read or write operations. Each 16-bit timer has a single 8-bit register for temporary storing of the high byte of the 16-bit access ...

  • Page 101

    ... Save global interrupt flag */ sreg = SREG; /* Disable interrupts */ _CLI(); /* Read TCNT1 into TCNT1; /* Restore global interrupt flag */ SREG = sreg; return i; } Note: 1. See “About Code Examples” on page 7. The assembly code example returns the TCNT1 value in the r17:r16 register pair. ATmega8515(L) 101 ...

  • Page 102

    ... Reusing the Temporary High Byte Register ATmega8515(L) 102 The following code examples show how atomic write of the TCNT1 Register contents. Writing any of the OCR1A/B or ICR1 Registers can be done by using the same principle. (1) Assembly Code Example TIM16_WriteTCNT1: ; Save global interrupt flag in r18,SREG ...

  • Page 103

    ... The counting sequence is determined by the setting of the Waveform Generation mode bits (WGM13:0) located in the Timer/Counter Control Registers A and B (TCCR1A and TCCR1B). There are close connections between how the counter behaves (counts) and ATmega8515(L) Count Control Logic Clear ) ...

  • Page 104

    ... Input Capture Unit ATmega8515(L) 104 how waveforms are generated on the Output Compare outputs OC1x. For more details about advanced counting sequences and waveform generation, see “Modes of Opera- tion” on page 109. The Timer/Counter Overflow (TOV1) Flag is set according to the mode of operation selected by the WGM13:0 bits ...

  • Page 105

    ... Measurement of an external signal’s duty cycle requires that the trigger edge is changed after each capture. Changing the edge sensing must be done as early as possible after the ICR1 Register has been read. After a change of the edge, the Input Capture Flag (ICF1) must be cleared by software (writing a logical one to the I/O bit location). For ATmega8515(L) 105 ...

  • Page 106

    ... Output Compare Units ATmega8515(L) 106 measuring frequency only, the clearing of the ICF1 Flag is not required (if an interrupt handler is used). The 16-bit comparator continuously compares TCNT1 with the Output Compare Regis- ter (OCR1x). If TCNT equals OCR1x the comparator signals a match. A match will set the Output Compare Flag (OCF1x) at the next timer clock cycle ...

  • Page 107

    ... Output Compare (FOC1x) strobe bits in Normal mode. The OC1x Register keeps its value even when changing between Waveform Generation modes. Be aware that the COM1x1:0 bits are not double buffered together with the compare value. Changing the COM1x1:0 bits will take effect immediately. ATmega8515(L) 107 ...

  • Page 108

    ... Compare Match Output Unit ATmega8515(L) 108 The Compare Output mode (COM1x1:0) bits have two functions. The Waveform Gener- ator uses the COM1x1:0 bits for defining the Output Compare (OC1x) state at the next Compare Match. Secondly the COM1x1:0 bits control the OC1x pin output source. Fig- ure 51 shows a simplified schematic of the logic affected by the COM1x1:0 bit setting ...

  • Page 109

    ... The output compare units can be used to generate interrupts at some given time. Using the output compare to generate waveforms in Normal mode is not recommended, since this will occupy too much of the CPU time. ATmega8515(L) 109 ...

  • Page 110

    ... Clear Timer on Compare Match (CTC) Mode ATmega8515(L) 110 In clear timer on compare or CTC mode (WGM13 12), the OCR1A or ICR1 Reg- ister are used to manipulate the counter resolution. In CTC mode the counter is cleared to zero when the counter value (TCNT1) matches either the OCR1A (WGM13 the ICR1 (WGM13:0 = 12) ...

  • Page 111

    ... The Timer/Counter Overflow Flag (TOV1) is set each time the counter reaches TOP. In addition the OC1A or ICF1 Flag is set at the same timer clock cycle as TOV1 is set when either OCR1A or ICR1 is used for defining the TOP value. If one of the interrupts ATmega8515( log TOP ...

  • Page 112

    ... ATmega8515(L) 112 are enabled, the interrupt handler routine can be used for updating the TOP and com- pare values. When changing the TOP value the program must ensure that the new TOP value is higher or equal to the value of all of the compare registers. If the TOP value is lower than any of the compare registers, a Compare Match will never occur between the TCNT1 and the OCR1x ...

  • Page 113

    ... PWM outputs. The small horizontal line marks on the TCNT1 slopes repre- sent Compare Matches between OCR1x and TCNT1. The OC1x Interrupt Flag will be set when a Compare Match occurs. Figure 54. Phase Correct PWM Mode, Timing Diagram TCNTn OCnx OCnx Period 1 ATmega8515( log + 1 TOP = ---------------------------------- - ...

  • Page 114

    ... ATmega8515(L) 114 The Timer/Counter Overflow Flag (TOV1) is set each time the counter reaches BOT- TOM. When either OCR1A or ICR1 is used for defining the TOP value, the OC1A or ICF1 Flag is set accordingly at the same timer clock cycle as the OCR1x Registers are updated with the double buffer value (at TOP). The Interrupt Flags can be used to gen- erate an interrupt each time the counter reaches the TOP or BOTTOM value ...

  • Page 115

    ... PWM outputs. The small horizontal line marks on the TCNT1 slopes represent Compare Matches between OCR1x and TCNT1. The OC1x Interrupt Flag will be set when a Com- pare Match occurs. Figure 55. Phase and Frequency Correct PWM Mode, Timing Diagram TCNTn OCnx OCnx Period 1 2 ATmega8515( log TOP + 1 = ---------------------------------- - ...

  • Page 116

    ... ATmega8515(L) 116 The Timer/Counter Overflow Flag (TOV1) is set at the same timer clock cycle as the OCR1x Registers are updated with the double buffer value (at BOTTOM). When either OCR1A or ICR1 is used for defining the TOP value, the OC1A or ICF1 Flag set when TCNT1 has reached TOP. The Interrupt Flags can then be used to generate an interrupt each time the counter reaches the TOP or BOTTOM value ...

  • Page 117

    ... PWM mode the OCR1x Register is updated at BOTTOM. The timing diagrams will be the same, but TOP should be replaced by BOTTOM, TOP-1 by BOTTOM+1 and so on. The same renaming applies for modes that set the TOV1 Flag at BOTTOM. ATmega8515(L) T1 OCRnx OCRnx + 1 OCRnx Value ...

  • Page 118

    ... ATmega8515(L) 118 Figure 58. Timer/Counter Timing Diagram, No Prescaling clk I/O clk Tn (clk /1) I/O TCNTn TOP - 1 (CTC and FPWM) TCNTn TOP - 1 (PC and PFC PWM) TOVn (FPWM) and ICFn (if used as TOP) OCRnx Old OCRnx Value (Update at TOP) Figure 59 shows the same timing data, but with the prescaler enabled. ...

  • Page 119

    ... In this case the Compare Match is ignored, but the set or clear is done at TOP. See “Fast PWM Mode” on page 111. for more details. Table 52 shows the COM1x1:0 bit functionality when the WGM13:0 bits are set to the phase correct or the phase and frequency correct, PWM mode. ATmega8515( ...

  • Page 120

    ... ATmega8515(L) 120 Table 52. Compare Output Mode, Phase Correct and Phase and Frequency Correct (1) PWM COM1A1/ COM1A0/ COM1B1 COM1B0 Description 0 0 Normal port operation, OC1A/OC1B disconnected WGM13 11: Toggle OC1A on Compare Match, OC1B disconnected (Normal port operation). For all other WGM1 setting, Normal port operation, OC1A/OC1B disconnected. ...

  • Page 121

    ... PWM, Phase and Frequency Correct 1 0 PWM, Phase Correct 1 1 PWM, Phase Correct 0 0 CTC 0 1 Reserved 1 0 Fast PWM 1 1 Fast PWM ATmega8515(L) Update of x TOP OCR1 at 0xFFFF Immediate 0x00FF TOP 0x01FF TOP 0x03FF TOP OCR1A Immediate 0x00FF BOTTOM 0x01FF ...

  • Page 122

    ... Timer/Counter1 Control Register B – TCCR1B ATmega8515(L) 122 Bit ICNC1 ICES1 – Read/Write R/W R/W R Initial Value • Bit 7 – ICNC1: Input Capture Noise Canceler Setting this bit (to one) activates the Input Capture Noise Canceler. When the Noise Canceler is activated, the input from the Input Capture Pin (ICP1) is filtered. The filter function requires four successive equal valued samples of the ICP1 pin for changing its output ...

  • Page 123

    ... The Output Compare Registers are 16-bit in size. To ensure that both the high and low bytes are written simultaneously when the CPU writes to these registers, the access is performed using an 8-bit temporary High Byte Register (TEMP). This temporary register is shared by all the other 16-bit registers. See “Accessing 16-bit Registers” on page 100. ATmega8515( ...

  • Page 124

    ... Input Capture Register 1 – ICR1H and ICR1L Timer/Counter Interrupt Mask (1) Register – TIMSK ATmega8515(L) 124 Bit Read/Write R/W R/W R/W Initial Value The Input Capture is updated with the counter (TCNT1) value each time an event occurs on the ICP1 pin (or optionally on the Analog Comparator output for Timer/Counter1). ...

  • Page 125

    ... Register (ICR1) is set by the WGM13 used as the TOP value, the ICF1 Flag is set when the counter reaches the TOP value. ICF1 is automatically cleared when the Input Capture Interrupt Vector is executed. Alter- natively, ICF1 can be cleared by writing a logic one to its bit location. ATmega8515( – ...

  • Page 126

    ... Serial Peripheral Interface – SPI ATmega8515(L) 126 The Serial Peripheral Interface (SPI) allows high-speed synchronous data transfer between the ATmega8515 and peripheral devices or between several AVR devices. The ATmega8515 SPI includes the following features: • Full Duplex, 3-wire Synchronous Data Transfer • ...

  • Page 127

    ... When the SPI is enabled, the data direction of the MOSI, MISO, SCK, and SS pins is overridden according to Table 55. For more details on automatic port overrides, refer to “Alternate Port Functions” on page 64. (1) Table 55. SPI Pin Overrides Pin Direction, Master SPI MOSI User Defined ATmega8515(L) MSB SLAVE MISO MISO 8-BIT SHIFT REGISTER MOSI MOSI SHIFT ...

  • Page 128

    ... ATmega8515(L) 128 (1) Table 55. SPI Pin Overrides Pin Direction, Master SPI MISO Input SCK User Defined SS User Defined Note: 1. See “Alternate Functions Of Port B” on page 67 for a detailed description of how to define the direction of the user defined SPI pins. The following code examples show how to initialize the SPI as a Master and how to per- form a simple transmission ...

  • Page 129

    ... DDR_SPI = (1<<DD_MOSI)|(1<<DD_SCK); /* Enable SPI, Master, set clock rate fck/16 */ SPCR = (1<<SPE)|(1<<MSTR)|(1<<SPR0); } void SPI_MasterTransmit(char cData Start transmission */ SPDR = cData; /* Wait for transmission complete */ while(!(SPSR & (1<<SPIF))) ; } Note: 1. See “About Code Examples” on page 7. ATmega8515(L) 129 ...

  • Page 130

    ... ATmega8515(L) 130 The following code examples show how to initialize the SPI as a Slave and how to per- form a simple reception. (1) Assembly Code Example SPI_SlaveInit: ; Set MISO output, all others input ldi r17,(1<<DD_MISO) out DDR_SPI,r17 ; Enable SPI ldi r17,(1<<SPE) ...

  • Page 131

    ... When the DORD bit is written to zero, the MSB of the data word is transmitted first. • Bit 4 – MSTR: Master/Slave Select This bit selects Master SPI mode when written to one, and Slave SPI mode when written logic zero configured as an input and is driven low while MSTR is set, MSTR will ATmega8515( ...

  • Page 132

    ... ATmega8515(L) 132 be cleared, and SPIF in SPSR will become set. The user will then have to set MSTR to re-enable SPI Master mode. • Bit 3 – CPOL: Clock Polarity When this bit is written to one, SCK is high when idle. When CPOL is written to zero, SCK is low when idle. Refer to Figure 62 and Figure 63 for an example. The CPOL func- tionality is summarized below: Table 56 ...

  • Page 133

    ... WCOL set, and then accessing the SPI Data Register. • Bit 5..1 – Res: Reserved Bits These bits are reserved bits in the ATmega8515 and will always read as zero. • Bit 0 – SPI2X: Double SPI Speed Bit When this bit is written logic one the SPI speed (SCK Frequency) will be doubled when the SPI is in Master mode (see Table 58) ...

  • Page 134

    ... Data Modes ATmega8515(L) 134 There are four combinations of SCK phase and polarity with respect to serial data, which are determined by control bits CPHA and CPOL. The SPI data transfer formats are shown in Figure 62 and Figure 63. Data bits are shifted out and latched in on oppo- site edges of the SCK signal, ensuring sufficient time for data signals to stabilize ...

  • Page 135

    ... Multi-processor Communication Mode • Double Speed Asynchronous Communication Mode The ATmega8515 has one USART. The functionality for the USART is described below. Note that in AT90S4414/8515 compatibility mode, the double buffering of the USART Receive Register is disabled. For details, see “AVR USART vs. AVR UART – Compati- bility” ...

  • Page 136

    ... ATmega8515(L) 136 Figure 64. USART Block Diagram UBRR[H:L] BAUD RATE GENERATOR UDR (Transmit) TRANSMIT SHIFT REGISTER RECEIVE SHIFT REGISTER UDR (Receive) UCSRA Note: 1. Refer to Figure 1 on page 2, Table 37 on page 73, and Table 31 on page 69 for USART pin placement. The dashed boxes in the block diagram separate the three main parts of the USART (listed from the top): Clock Generator, Transmitter and Receiver ...

  • Page 137

    ... The XCK pin is only active when using Synchronous mode. Figure 65 shows a block diagram of the clock generation logic. Figure 65. Clock Generation Logic, Block Diagram UBRR UBRR+1 Prescaling Down-counter OSC Sync Register xcki XCK xcko Pin DDR_XCK ATmega8515(L) fosc / DDR_XCK Edge Detector UCPOL U2X txclk 1 0 ...

  • Page 138

    ... Internal Clock Generation – The Baud Rate Generator ATmega8515(L) 138 Signal description: txclk Transmitter clock. (Internal Signal) rxclk Receiver base clock. (Internal Signal) xcki Input from XCK pin (internal Signal). Used for synchronous slave operation. xcko Clock output to XCK pin (Internal Signal). Used for synchronous master operation ...

  • Page 139

    ... The UCPOL bit UCRSC selects which XCK clock edge is used for data sampling and which is used for data change. As Figure 66 shows, when UCPOL is zero the data will be changed at rising XCK edge and sampled at falling XCK edge. If UCPOL is set, the data will be changed at falling XCK edge and sampled at rising XCK edge. ATmega8515(L) f OSC < ...

  • Page 140

    ... Frame Formats Parity Bit Calculation ATmega8515(L) 140 A serial frame is defined to be one character of data bits with synchronization bits (start and stop bits), and optionally a parity bit for error checking. The USART accepts all 30 combinations of the following as valid frame formats: • 1 start bit • ...

  • Page 141

    ... Set baud rate */ UBRRH = (unsigned char)(baud>>8); UBRRL = (unsigned char)baud; /* Enable receiver and transmitter */ UCSRB = (1<<RXEN)|(1<<TXEN); /* Set frame format: 8data, 2stop bit */ UCSRC = (1<<URSEL)|(1<<USBS)|(3<<UCSZ0); } Note: 1. See “About Code Examples” on page 7. ATmega8515(L) 141 ...

  • Page 142

    ... Data Transmission – The USART Transmitter Sending Frames with Data Bits ATmega8515(L) 142 More advanced initialization routines can be made that include frame format as parame- ters, disable interrupts and so on. However, many applications use a fixed setting of the Baud and Control Registers, and for these types of applications the initialization code can be placed directly in the main routine combined with initialization code for other I/O modules ...

  • Page 143

    ... Register. For compatibility with future devices, always write this bit to zero when writing the UCSRA Register. When the Data Register Empty Interrupt Enable (UDRIE) bit in UCSRB is written to one, the USART Data Register Empty Interrupt will be executed as long as UDRE is set (pro- vided that global interrupts are enabled). UDRE is cleared by writing UDR. When ATmega8515(L) 143 ...

  • Page 144

    ... Parity Generator Disabling the Transmitter ATmega8515(L) 144 interrupt-driven data transmission is used, the Data Register Empty Interrupt routine must either write new data to UDR in order to clear UDRE or disable the Data Register Empty Interrupt, otherwise a new interrupt will occur once the interrupt routine terminates ...

  • Page 145

    ... UDR I/O location will change the state of the receive buffer FIFO and consequently the TXB8, FE, DOR, and PE bits, which all are stored in the FIFO, will change. The following code example shows a simple USART receive function that handles both 9-bit characters and the status bits. ATmega8515(L) 145 ...

  • Page 146

    ... ATmega8515(L) 146 (1) Assembly Code Example USART_Receive: ; Wait for data to be received sbis UCSRA, RXC rjmp USART_Receive ; Get status and ninth bit, then data from buffer in r18, UCSRA in r17, UCSRB in r16, UDR ; If error, return -1 andi r18,(1<<FE)|(1<<DOR)|(1<<PE) ...

  • Page 147

    ... If parity check is not enabled the PE bit will always be read zero. For compatibility with future devices, always set this bit to zero when writing to UCSRA. For more details see “Parity Bit Calculation” on page 140 and “Parity Checker” on page 148. ATmega8515(L) 147 ...

  • Page 148

    ... Disabling the Receiver Flushing the Receive Buffer Asynchronous Data Reception ATmega8515(L) 148 The Parity Checker is active when the high USART Parity mode (UPM1) bit is set. Type of parity check to be performed (odd or even) is selected by the UPM0 bit. When enabled, the parity checker calculates the parity of the data bits in incoming frames and compares the result with the parity bit from the serial frame ...

  • Page 149

    ... This majority voting process acts as a low pass filter for the incoming signal on the RxD pin. The recovery process is then repeated until a complete frame is received. Including the first stop bit. Note that the Receiver only uses the first stop bit of a frame. ATmega8515(L) START 6 7 ...

  • Page 150

    ... Asynchronous Operational Range ATmega8515(L) 150 Figure 70 shows the sampling of the stop bit and the earliest possible beginning of the start bit of the next frame. Figure 70. Stop Bit Sampling and Next Start Bit Sampling RxD Sample (U2X = 0) Sample (U2X = The same majority voting is done to the stop bit as done for the other bits in the frame. If the stop bit is registered to have a logic 0 value, the Frame Error (FE) Flag will be set ...

  • Page 151

    ... When the frame type bit (the first stop or the ninth bit) is one, the frame contains an address. When the frame type bit is zero the frame is a data frame. ATmega8515(L) Max Total Recommended Max ...

  • Page 152

    ... Using MPCM ATmega8515(L) 152 The Multi-processor Communication mode enables several Slave MCUs to receive data from a Master MCU. This is done by first decoding an address frame to find out which MCU has been addressed particular Slave MCU has been addressed, it will receive the following data frames as normal, while the other Slave MCUs will ignore the received frames until another address frame is received ...

  • Page 153

    ... Set the USBS and the UCSZ1 bit to one, and */ /* the remaining bits to zero. */ UCSRC = (1<<URSEL)|(1<<USBS)|(1<<UCSZ1); ... Note: 1. See “About Code Examples” on page 7. As the code examples illustrate, write accesses of the two registers are relatively unaf- fected of the sharing of I/O location. ATmega8515(L) 153 ...

  • Page 154

    ... Read Access ATmega8515(L) 154 Doing a read access to the UBRRH or the UCSRC Register is a more complex opera- tion. However, in most applications rarely necessary to read any of these registers. The read access is controlled by a timed sequence. Reading the I/O location once returns the UBRRH Register contents. If the register location was read in previous sys- tem clock cycle, reading the register in the current clock cycle will return the UCSRC contents ...

  • Page 155

    ... The UDRE Flag indicates if the transmit buffer (UDR) is ready to receive new data. If UDRE is one, the buffer is empty, and therefore ready to be written. The UDRE Flag can generate a Data Register Empty interrupt (see description of the UDRIE bit). UDRE is set after a reset to indicate that the Transmitter is ready. • Bit 4 – FE: Frame Error ATmega8515( ...

  • Page 156

    ... USART Control and Status Register B – UCSRB ATmega8515(L) 156 This bit is set if the next character in the receive buffer had a Frame Error when received. For example, when the first stop bit of the next character in the receive buffer is zero. This bit is valid until the receive buffer (UDR) is read. The FE bit is zero when the stop bit of received data is one. Always set this bit to zero when writing to UCSRA. • ...

  • Page 157

    ... These bits enable and set type of parity generation and check. If enabled, the Transmit- ter will automatically generate and send the parity of the transmitted data bits within each frame. The Receiver will generate a parity value for the incoming data and com- pare it to the UPM0 setting mismatch is detected, the PE Flag in UCSRA will be set. ATmega8515( ...

  • Page 158

    ... ATmega8515(L) 158 Table 64. UPM Bits Settings UPM1 UPM0 • Bit 3 – USBS: Stop Bit Select This bit selects the number of stop bits to be inserted by the Transmitter. The Receiver ignores this setting. Table 65. USBS Bit Settings USBS 0 1 • Bit 2:1 – UCSZ1:0: Character Size The UCSZ1:0 bits combined with the UCSZ2 bit in UCSRB sets the number of data bits (character size frame the Receiver and Transmitter use ...

  • Page 159

    ... Higher error ratings are acceptable, but the Receiver will have less noise resistance when the error ratings are high, especially for large serial frames (see “Asynchronous Operational Range” on page 150). The error values are cal- culated using the following equation: ⎛ Error[%] = ⎝ ATmega8515( – UBRR[11:8] UBRR[7:0] ...

  • Page 160

    ... Max. 62.5 kbps 125 kbps 1. UBRR = 0, Error = 0.0% ATmega8515(L) 160 f = 1.8432 MHz osc U2X = 0 U2X = 1 Error UBRR Error UBRR 0.2% 47 0.0% 95 0.2% 23 0.0% 47 0.2% 11 0.0% 23 -3. ...

  • Page 161

    ... ATmega8515( 7.3728 MHz osc U2X = 1 U2X = 0 UBRR Error UBRR Error 207 0.2% 191 0.0% 103 0.2% 95 0.0% 51 0.2% 47 0.0% 34 -0. ...

  • Page 162

    ... Max. 0.5 Mbps 1. UBRR = 0, Error = 0.0% ATmega8515(L) 162 11.0592 f = osc U2X = 0 Error UBRR Error UBRR -0.1% 287 0.0% 0.2% 143 0.0% 0.2% 71 0.0% 0.6% 47 0.0% 0.2% 35 0.0% -0.8% 23 0.0% ...

  • Page 163

    ... Mbps 1.152 Mbps ATmega8515( 20.0000 MHz osc U2X = 1 U2X = 0 UBRR Error UBRR Error 959 0.0% 520 0.0% 479 0.0% 259 0.2% 239 0.0% 129 0.2% 159 ...

  • Page 164

    ... Analog Comparator Analog Comparator Control and Status Register – ACSR ATmega8515(L) 164 The Analog Comparator compares the input values on the positive pin AIN0 and nega- tive pin AIN1. When the voltage on the positive pin AIN0 is higher than the voltage on the negative pin AIN1, the Analog Comparator Output, ACO, is set. The comparator’s output can be set to trigger the Timer/Counter1 Input Capture function ...

  • Page 165

    ... Comparator Interrupt on Falling Output Edge 1 1 Comparator Interrupt on Rising Output Edge When changing the ACIS1/ACIS0 bits, the Analog Comparator interrupt must be dis- abled by clearing its Interrupt Enable bit in the ACSR Register. Otherwise an interrupt can occur when the bits are changed. ATmega8515(L) 165 ...

  • Page 166

    ... BLS – Boot Loader Section Read-While-Write and No Read-While-Write Flash Sections ATmega8515(L) 166 The Boot Loader Support provides a real Read-While-Write Self-Programming mecha- nism for downloading and uploading program code by the MCU itself. This feature allows flexible application software updates controlled by the MCU using a Flash-resi- dent Boot Loader program ...

  • Page 167

    ... Programming? RWW section NRWW section Figure 72. Read-While-Write vs. No Read-While-Write Read-While-Write Z-pointer Addresses RWW No Read-While-Write Section Code Located in NRWW Section Can be Read during the Operation ATmega8515(L) Read during Is the CPU Programming? Halted? NRWW section No None Yes (RWW) Section Z-pointer Addresses NRWW Section ...

  • Page 168

    ... Boot Loader Lock bits ATmega8515(L) 168 (1) Figure 73. Memory Sections Program Memory BOOTSZ = '11' $0000 Application Flash Section End RWW Start NRWW Application Flash Section End Application Start Boot Loader Boot Loader Flash Section Flashend Program Memory BOOTSZ = '01' $0000 Application Flash Section End RWW ...

  • Page 169

    ... Reset Vector = Application Reset (address $0000) 0 Reset Vector = Boot Loader Reset (see Table 78 on page 177) Note: 1. “1” means unprogrammed, “0” means programmed ATmega8515(L) (1) Protection No restrictions for SPM or LPM accessing the Application section. SPM is not allowed to write to the Application section. ...

  • Page 170

    ... RWWSB bit will automatically be cleared if a page load operation is initiated. • Bit 5 – Res: Reserved Bit This bit is a reserved bit in the ATmega8515 and always read as zero. • Bit 4 – RWWSRE: Read-While-Write Section Read Enable When programming (page erase or page write) to the RWW section, the RWW section is blocked for reading (the RWWSB will be set by hardware) ...

  • Page 171

    ... The only SPM operation that does not use the Z-pointer is Setting the Boot Loader Lock bits. The content of the Z-pointer is ignored and will have no effect on the operation. The LPM instruction does also use the Z-pointer to store the address. Since this instruction addresses the Flash byte by byte, also the LSB (bit Z0) of the Z-pointer is used. ATmega8515( ...

  • Page 172

    ... Self-Programming the Flash ATmega8515(L) 172 Figure 74. Addressing the Flash during SPM BIT 15 ZPCMSB Z - REGISTER PCMSB PROGRAM PCPAGE COUNTER PAGE ADDRESS WITHIN THE FLASH PROGRAM MEMORY PAGE Notes: 1. The different variables used in Figure 74 are listed in Table 80 on page 178. 2. PCPAGE and PCWORD are listed in Table 89 on page 183. ...

  • Page 173

    ... BLS as described in “Interrupts” on page 54, or the inter- rupts must be disabled. Before addressing the RWW section after the programming is completed, the user software must clear the RWWSB by writing the RWWSRE. See “Simple Assembly Code Example for a Boot Loader” on page 175 for an example. ATmega8515(L) 173 ...

  • Page 174

    ... EEPROM Write Prevents Writing to SPMCR Reading the Fuse and Lock bits from Software ATmega8515(L) 174 To set the Boot Loader Lock bits, write the desired data to R0, write “X0001001” to SPMCR and execute SPM within four clock cycles after writing SPMCR. The only accessible Lock bits are the Boot Lock bits that may prevent the Application and Boot Loader section from any software update by the MCU ...

  • Page 175

    ... Boot ; loader section or that the interrupts are disabled. .equ PAGESIZEB = PAGESIZE*2 words .org SMALLBOOTSTART Write_page: ; page erase ldi spmcrval, (1<<PGERS) | (1<<SPMEN) rcallDo_spm ATmega8515(L) Min Programming Time Max Programming Time 3.7 ms ;PAGESIZEB is page size in BYTES, not CC . This CC 4.5 ms 175 ...

  • Page 176

    ... ATmega8515(L) 176 ; re-enable the RWW section ldi spmcrval, (1<<RWWSRE) | (1<<SPMEN) rcallDo_spm ; transfer data from RAM to Flash page buffer ldi looplo, low(PAGESIZEB) ldi loophi, high(PAGESIZEB) Wrloop r1, Y+ ldi spmcrval, (1<<SPMEN) rcallDo_spm adiw ZH:ZL, 2 sbiw loophi:looplo, 2 brne Wrloop ; execute page write ...

  • Page 177

    ... ATmega8515 Boot Loader Parameters 2512K–AVR–01/10 ; input: spmcrval determines SPM action ; disable interrupts if enabled, store status in temp2, SREG cli ; check that no EEPROM write access is present Wait_ee: sbic EECR, EEWE rjmp Wait_ee ; SPM timed sequence out SPMCR, spmcrval spm ; restore SREG (to enable interrupts if originally enabled) ...

  • Page 178

    ... ATmega8515(L) 178 Table 80. Explanation of Different Variables used in Figure 74 and the Mapping to the (1) Z-pointer Corresponding Variable Z-value PCMSB 11 PAGEMSB 4 ZPCMSB Z12 ZPAGEMSB Z5 PCPAGE PC[11:5] Z12:Z6 PCWORD PC[4:0] Z5:Z1 Note: 1. Z15:Z13: always ignored. Z0: should be zero for all SPM commands, byte select for the LPM instruction. ...

  • Page 179

    ... Memory Lock bits 2512K–AVR–01/10 The ATmega8515 provides six Lock bits which can be left unprogrammed (“1”) or can be programmed (“0”) to obtain the additional features listed in Table 82. The Lock bits can only be erased to “1” with the Chip Erase command. ...

  • Page 180

    ... Program the Fuse bits before programming the Lock bits. 2. “1” means unprogrammed, “0” means programmed The ATmega8515 has two Fuse bytes. Table 83 and Table 84 describe briefly the func- tionality of all the fuses and how they are mapped into the fuse bytes. Note that the Fuses are read as logical zero, “ ...

  • Page 181

    ... Flash memory). 3. $002: $06 (indicates ATmega8515 device when $001 is $93). The ATmega8515 stores four different calibration values for the internal RC Oscillator. These bytes resides in the signature row high byte of the addresses 0x000, 0x0001, 0x0002, and 0x0003 for and 8 MHz respectively. During Reset, the 1 MHz value is automatically loaded into the OSCCAL Register. If other frequencies are used, the calibration value has to be loaded manually, see “ ...

  • Page 182

    ... EEPROM Data memory, Memory Lock bits, and Fuse bits in the ATmega8515. Pulses are assumed least 250 ns unless otherwise noted. In this section, some pins of the ATmega8515 are referenced by signal names describ- ing their functionality during parallel programming, see Figure 75 and Table 85. Pins not described in the following table are referenced by pin names ...

  • Page 183

    ... Table 89. No. of Words in a Page and No. of Pages in the Flash Flash Size Page Size 4K words (8K bytes) 32 words Table 90. No. of Words in a Page and No. of Pages in the EEPROM EEPROM Size Page Size 512 bytes 4 bytes ATmega8515(L) Symbol Prog_enable[3] Prog_enable[2] Prog_enable[1] Prog_enable[0] PCWORD No. of Pages PCPAGE PC[4:0] ...

  • Page 184

    ... Parallel Programming Enter Programming Mode Considerations for Efficient Programming Chip Erase ATmega8515(L) 184 The following algorithm puts the device in Parallel Programming mode: 1. Apply 4.5 - 5.5 V between Set RESET to “0”, wait for at least 100 ns and toggle XTAL1 at least six times. 3. Set the Prog_enable pins listed in Table 86 on page 183 to “0000” and wait at least 100 ns ...

  • Page 185

    ... Set BS1 to “1”. This selects high address. 3. Set DATA = Address high byte ($00 - $FF). 4. Give XTAL1 a positive pulse. This loads the address high byte. H. Program Page 1. Set BS1 = “0”. 2. Give WR a negative pulse. This starts programming of the entire page of data. RDY/BSY goes low. ATmega8515(L) 185 ...

  • Page 186

    ... ATmega8515(L) 186 3. Wait until RDY/BSY goes high. (See Figure 77 for signal waveforms) I. Repeat B through H until the entire Flash is programmed or until all data has been programmed. J. End Page Programming 1. 1. Set XA1, XA0 to “10”. This enables command loading. 2. Set DATA to “0000 0000”. This is the command for No Operation. ...

  • Page 187

    ... K: Repeat 3 through 5 until the entire buffer is filled. L: Program EEPROM page. 1. Set BS1 to “0”. 2. Give WR a negative pulse. This starts programming of the EEPROM page. RDY/BSY goes low. 3. Wait until to RDY/BSY goes high before programming the next page. (See Figure 78 for signal waveforms.) ATmega8515( ...

  • Page 188

    ... Reading the Flash Reading the EEPROM Programming the Fuse Low Bits Programming the Fuse High Bits ATmega8515(L) 188 Figure 78. Programming the EEPROM Waveforms $11 ADDR. HIGH ADDR. LOW DATA XA1 XA0 BS1 XTAL1 WR RDY/BSY RESET +12V OE PAGEL BS2 The algorithm for reading the Flash memory is as follows (refer to “Programming the Flash” ...

  • Page 189

    ... Set OE to “0”, BS2 to “1” and BS1 to “1”. The status of the Fuse High bits can now be read at DATA (“0” means programmed). 4. Set OE to “0”, BS2 to “0” and BS1 to “1”. The status of the Lock bits can now be read at DATA (“0” means programmed). 5. Set OE to “1”. ATmega8515( $40 ...

  • Page 190

    ... Reading the Signature Bytes Reading the Calibration Byte Parallel Programming Characteristics ATmega8515(L) 190 Figure 80. Mapping Between BS1, BS2, and the Fuse- and Lock bits During Read Fuse Low Byte Lock Bits Fuse High Byte BS2 The algorithm for reading the Signature bytes is as follows (refer to “Programming the Flash” ...

  • Page 191

    ... Data and Control Valid before XTAL1 High DVXH t XTAL1 Low to XTAL1 High XLXH t XTAL1 Pulse Width High XHXL t Data and Control Hold after XTAL1 Low XLDX ATmega8515(L) LOAD DATA LOAD DATA (HIGH BYTE XLPH t XLXH PLXH DATA (Low Byte) DATA (High Byte) ...

  • Page 192

    ... ATmega8515(L) 192 Table 91. Parallel Programming Characteristics, V Symbol Parameter t XTAL1 Low to WR Low XLWL t XTAL1 Low to PAGEL high XLPH t PAGEL low to XTAL1 high PLXH t BS1 Valid before PAGEL High BVPH t PAGEL Pulse Width High PHPL t BS1 Hold after PAGEL Low PLBX t BS2/1 Hold after WR Low ...

  • Page 193

    ... Depending on CKSEL Fuses, a valid clock must be present. The minimum low and high periods for the serial clock (SCK) input are defined as follows: Low: > 2 CPU clock cycles for f ck High: > 2 CPU clock cycles for f ck ATmega8515(L) I/O Description I Serial data in O ...

  • Page 194

    ... Data Polling Flash ATmega8515(L) 194 When writing serial data to the ATmega8515, data is clocked on the rising edge of SCK. When reading data from the ATmega8515, data is clocked on the falling edge of SCK. See Figure 85 for timing details. To program and verify the ATmega8515 in the Serial Programming mode, the following sequence is recommended (See four byte instruction formats in Table 94 ...

  • Page 195

    ... Table 93. Minimum Wait Delay Before Writing the Next Flash or EEPROM Location Symbol t WD_FUSE t WD_FLASH t WD_EEPROM t WD_ERASE Figure 85. Serial Programming Waveforms SERIAL DATA INPUT MSB (MOSI) SERIAL DATA OUTPUT MSB (MISO) SERIAL CLOCK INPUT (SCK) SAMPLE ATmega8515(L) value. WD_EEPROM Minimum Wait Delay 4.5 ms 4.5 ms 9.0 ms 9.0 ms LSB LSB 195 ...

  • Page 196

    ... Read Fuse High Bits Read Calibration Byte 0011 1000 Note address high bits b = address low bits Low byte High Byte o = data out i = data don’t care ATmega8515(L) 196 Instruction Format Byte 2 Byte 3 Byte4 0101 0011 xxxx xxxx xxxx xxxx 100x xxxx ...

  • Page 197

    ... V, pin high CC (absolute value ATmega8515(L) Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent dam- age to the device. This is a stress rating only and functional operation of the device at these or other conditions beyond those indicated in the operational sections of this specification is not implied ...

  • Page 198

    ... The sum of all IOH,for ports D7, and XTAL2,should not exceed 100 mA. 3] The sum of all IOH,for ports E2, and should not exceed 100 mA. 5. Minimum V for Power-down is 2.5V. CC ATmega8515(L) 198 Condition Min Active 4 MHz ATmega8515 ( L) Active 8 MHz ATmega8515 ( ) Idle 4 MHz ATmega8515 ( L) Idle 8 MHz ATmega8515 ( ) WDT enabled WDT disabled - 2. ...

  • Page 199

    ... R should be in the range 3 kΩ - 100 kΩ, and C should be at least 20 pF. The C values given in the table includes pin capacitance. This will vary with package type. 2. The frequency will vary with package type and board layout. ATmega8515(L) 5.5 5 ...

  • Page 200

    ... SPI Timing Characteristics ATmega8515(L) 200 See Figure 87 and Figure 88 for details. Table 97. SPI Timing Parameters Description Mode 1 SCK period Master 2 SCK high/low Master 3 Rise/Fall time Master 4 Setup Master 5 Hold Master 6 Out to SCK Master 7 SCK to out Master 8 SCK to out high Master 9 SS low to out ...