ATMEGA8515-16AI Atmel, ATMEGA8515-16AI Datasheet - Page 57

• Manufacturer Part Number: ATMEGA8515-16AI
• Description: IC AVR MCU 8K 16MHZ IND 44-TQFP
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA8515-16AI

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: EBI/EMI, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 35
• Program Memory Size: 8KB (4K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-TQFP, 44-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Data Converters: -

Moving Interrupts between
Application and Boot Space
General Interrupt Control
Register – GICR
2512K–AVR–01/10
The General Interrupt Control Register controls the placement of the Interrupt Vector
table.
• Bit 1 – IVSEL: Interrupt Vector Select
When the IVSEL bit is cleared (zero), the Interrupt Vectors are placed at the start of the
Flash memory. When this bit is set (one), the Interrupt Vectors are moved to the begin-
ning of the Boot Loader section of the Flash. The actual address of the start of the Boot
Flash section is determined by the BOOTSZ Fuses. Refer to the section “Boot Loader
Support – Read-While-Write Self-Programming” on page 166 for details. To avoid unin-
tentional changes of Interrupt Vector tables, a special write procedure must be followed
to change the IVSEL bit:
1. Write the Interrupt Vector Change Enable (IVCE) bit to one.
2. Within four cycles, write the desired value to IVSEL while writing a zero to IVCE.
Interrupts will automatically be disabled while this sequence is executed. Interrupts are
disabled in the cycle IVCE is set, and they remain disabled until after the instruction fol-
lowing the write to IVSEL. If IVSEL is not written, interrupts remain disabled for four
cycles. The I-bit in the Status Register is unaffected by the automatic disabling.
Note:
Bit
Read/Write
Initial Value
$C12
$C13
$C14
$C15
$C16
If Interrupt Vectors are placed in the Boot Loader section and Boot Lock bit BLB02 is pro-
grammed, interrupts are disabled while executing from the Application section. If
Interrupt Vectors are placed in the Application section and Boot Lock bit BLB12 is pro-
gramed, interrupts are disabled while executing from the Boot Loader section. Refer to
the section “Boot Loader Support – Read-While-Write Self-Programming” on page 166
for details on Boot Lock bits.
INT1
R/W
7
0
INT0
R/W
out
ldi
out
sei
<instr>
6
0
SPH,r16
r16,low(RAMEND)
SPL,r16
INT2
R/W
5
0
xxx
R
4
–
0
; Set Stack Pointer to top of RAM
; Enable interrupts
R
3
–
0
ATmega8515(L)
R
2
–
0
IVSEL
R/W
1
0
IVCE
R/W
0
0
GICR
57