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ATMEGA8535L8AC
ATMEGA8535L8AC  

Manufacturer Part Number  ATMEGA8535L8AC 
Description  IC AVR MCU 8K LV 8MHZ COM 44TQFP 
Manufacturer  Atmel 
Series  AVR® ATmega 
ATMEGA8535L8AC datasheets 

Specifications of ATMEGA8535L8AC  

Core Processor  AVR  Core Size  8Bit 
Speed  8MHz  Connectivity  I²C, SPI, UART/USART 
Peripherals  Brownout Detect/Reset, POR, PWM, WDT  Number Of I /o  32 
Program Memory Size  8KB (4K x 16)  Program Memory Type  FLASH 
Eeprom Size  512 x 8  Ram Size  512 x 8 
Voltage  Supply (vcc/vdd)  2.7 V ~ 5.5 V  Data Converters  A/D 8x10b 
Oscillator Type  Internal  Operating Temperature  0°C ~ 70°C 
Package / Case  44TQFP, 44VQFP  Lead Free Status / RoHS Status  Contains lead / RoHS noncompliant 
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Instruction Set Summary
Mnemonics
Operands
Description
ARITHMETIC AND LOGIC INSTRUCTIONS
ADD
Rd, Rr
Add two Registers
ADC
Rd, Rr
Add with Carry two Registers
ADIW
Rdl,K
Add Immediate to Word
SUB
Rd, Rr
Subtract two Registers
SUBI
Rd, K
Subtract Constant from Register
SBC
Rd, Rr
Subtract with Carry two Registers
SBCI
Rd, K
Subtract with Carry Constant from Reg.
SBIW
Rdl,K
Subtract Immediate from Word
AND
Rd, Rr
Logical AND Registers
ANDI
Rd, K
Logical AND Register and Constant
OR
Rd, Rr
Logical OR Registers
ORI
Rd, K
Logical OR Register and Constant
EOR
Rd, Rr
Exclusive OR Registers
COM
Rd
One’s Complement
NEG
Rd
Two’s Complement
SBR
Rd,K
Set Bit(s) in Register
CBR
Rd,K
Clear Bit(s) in Register
INC
Rd
Increment
DEC
Rd
Decrement
TST
Rd
Test for Zero or Minus
CLR
Rd
Clear Register
SER
Rd
Set Register
MUL
Rd, Rr
Multiply Unsigned
MULS
Rd, Rr
Multiply Signed
MULSU
Rd, Rr
Multiply Signed with Unsigned
FMUL
Rd, Rr
Fractional Multiply Unsigned
FMULS
Rd, Rr
Fractional Multiply Signed
FMULSU
Rd, Rr
Fractional Multiply Signed with Unsigned
BRANCH INSTRUCTIONS
RJMP
k
Relative Jump
IJMP
Indirect Jump to (Z)
RCALL
k
Relative Subroutine Call
ICALL
Indirect Call to (Z)
RET
Subroutine Return
RETI
Interrupt Return
CPSE
Rd,Rr
Compare, Skip if Equal
CP
Rd,Rr
Compare
CPC
Rd,Rr
Compare with Carry
CPI
Rd,K
Compare Register with Immediate
SBRC
Rr, b
Skip if Bit in Register Cleared
SBRS
Rr, b
Skip if Bit in Register is Set
SBIC
P, b
Skip if Bit in I/O Register Cleared
SBIS
P, b
Skip if Bit in I/O Register is Set
BRBS
s, k
Branch if Status Flag Set
BRBC
s, k
Branch if Status Flag Cleared
BREQ
k
Branch if Equal
BRNE
k
Branch if Not Equal
BRCS
k
Branch if Carry Set
BRCC
k
Branch if Carry Cleared
BRSH
k
Branch if Same or Higher
BRLO
k
Branch if Lower
BRMI
k
Branch if Minus
BRPL
k
Branch if Plus
BRGE
k
Branch if Greater or Equal, Signed
BRLT
k
Branch if Less Than Zero, Signed
BRHS
k
Branch if Half Carry Flag Set
BRHC
k
Branch if Half Carry Flag Cleared
BRTS
k
Branch if T Flag Set
BRTC
k
Branch if T Flag Cleared
BRVS
k
Branch if Overflow Flag is Set
BRVC
k
Branch if Overflow Flag is Cleared
BRIE
k
Branch if Interrupt Enabled
BRID
k
Branch if Interrupt Disabled
DATA TRANSFER INSTRUCTIONS
ATmega8535(L)
10
Operation
Flags
Rd ← Rd + Rr
Z,C,N,V,H
Rd ← Rd + Rr + C
Z,C,N,V,H
Rdh:Rdl ← Rdh:Rdl + K
Z,C,N,V,S
Rd ← Rd  Rr
Z,C,N,V,H
Rd ← Rd  K
Z,C,N,V,H
Rd ← Rd  Rr  C
Z,C,N,V,H
Rd ← Rd  K  C
Z,C,N,V,H
Rdh:Rdl ← Rdh:Rdl  K
Z,C,N,V,S
Rd ← Rd • Rr
Z,N,V
Rd ← Rd • K
Z,N,V
Rd ← Rd v Rr
Z,N,V
Rd ← Rd v K
Z,N,V
Rd ← Rd ⊕ Rr
Z,N,V
Rd ← 0xFF − Rd
Z,C,N,V
Rd ← 0x00 − Rd
Z,C,N,V,H
Rd ← Rd v K
Z,N,V
Rd ← Rd • (0xFF  K)
Z,N,V
Rd ← Rd + 1
Z,N,V
Rd ← Rd − 1
Z,N,V
Rd ← Rd • Rd
Z,N,V
Rd ← Rd ⊕ Rd
Z,N,V
Rd ← 0xFF
None
R1:R0 ← Rd x Rr
Z,C
R1:R0 ← Rd x Rr
Z,C
R1:R0 ← Rd x Rr
Z,C
<< 1
R1:R0 ← (Rd x Rr)
Z,C
R1:R0 ← (Rd x Rr)
<< 1
Z,C
<< 1
R1:R0 ← (Rd x Rr)
Z,C
PC ← PC + k + 1
None
PC ← Z
None
PC ← PC + k + 1
None
PC ← Z
None
PC ← STACK
None
PC ← STACK
I
if (Rd = Rr) PC ← PC + 2 or 3
None
Rd − Rr
Z, N,V,C,H
Rd − Rr − C
Z, N,V,C,H
Rd − K
Z, N,V,C,H
if (Rr(b)=0) PC ← PC + 2 or 3
None
if (Rr(b)=1) PC ← PC + 2 or 3
None
if (P(b)=0) PC ← PC + 2 or 3
None
if (P(b)=1) PC ← PC + 2 or 3
None
if (SREG(s) = 1) then PC←PC+k + 1
None
if (SREG(s) = 0) then PC←PC+k + 1
None
if (Z = 1) then PC ← PC + k + 1
None
if (Z = 0) then PC ← PC + k + 1
None
if (C = 1) then PC ← PC + k + 1
None
if (C = 0) then PC ← PC + k + 1
None
if (C = 0) then PC ← PC + k + 1
None
if (C = 1) then PC ← PC + k + 1
None
if (N = 1) then PC ← PC + k + 1
None
if (N = 0) then PC ← PC + k + 1
None
if (N ⊕ V= 0) then PC ← PC + k + 1
None
if (N ⊕ V= 1) then PC ← PC + k + 1
None
if (H = 1) then PC ← PC + k + 1
None
if (H = 0) then PC ← PC + k + 1
None
if (T = 1) then PC ← PC + k + 1
None
if (T = 0) then PC ← PC + k + 1
None
if (V = 1) then PC ← PC + k + 1
None
if (V = 0) then PC ← PC + k + 1
None
if ( I = 1) then PC ← PC + k + 1
None
if ( I = 0) then PC ← PC + k + 1
None
#Clocks
1
1
2
1
1
1
1
2
1
1
1
1
1
1
1
1
1
1
1
1
1
1
2
2
2
2
2
2
2
2
3
3
4
4
1 / 2 / 3
1
1
1
1 / 2 / 3
1 / 2 / 3
1 / 2 / 3
1 / 2 / 3
1 / 2
1 / 2
1 / 2
1 / 2
1 / 2
1 / 2
1 / 2
1 / 2
1 / 2
1 / 2
1 / 2
1 / 2
1 / 2
1 / 2
1 / 2
1 / 2
1 / 2
1 / 2
1 / 2
1 / 2
2502KS–AVR–10/06
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