AT89LS52-16PC Atmel, AT89LS52-16PC Datasheet - Page 12

• Manufacturer Part Number: AT89LS52-16PC
• Description: IC MCU 8K FLASH LV 16MHZ 40-DIP
• Manufacturer: Atmel
• Series: 89LSr

Specifications of AT89LS52-16PC

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: UART/USART
• Peripherals: WDT
• Number Of I /o: 32
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 4 V
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 40-DIP (0.600", 15.24mm)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Data Converters: -

8. UART
9. Timer 0 and 1
10. Timer 2
12
AT89LS52
The UART in the AT89LS52 operates the same way as the UART in the AT89C51 and
AT89C52. For further information on the UART operation, please click on the document link
below:
Timer 0 and Timer 1 in the AT89LS52 operate the same way as Timer 0 and Timer 1 in the
AT89C51 and AT89C52. For further information on the timers’ operation, please click on the
document link below:
Timer 2 is a 16-bit Timer/Counter that can operate as either a timer or an event counter. The
type of operation is selected by bit C/T2 in the SFR T2CON (shown in
three operating modes: capture, auto-reload (up or down counting), and baud rate generator.
The modes are selected by bits in T2CON, as shown in
registers, TH2 and TL2. In the Timer function, the TL2 register is incremented every machine
cycle. Since a machine cycle consists of 12 oscillator periods, the count rate is 1/12 of the oscil-
lator frequency.
Table 10-1.
In the Counter function, the register is incremented in response to a 1-to-0 transition at its corre-
sponding external input pin, T2. In this function, the external input is sampled during S5P2 of
every machine cycle. When the samples show a high in one cycle and a low in the next cycle,
the count is incremented. The new count value appears in the register during S3P1 of the cycle
following the one in which the transition was detected. Since two machine cycles (24 oscillator
periods) are required to recognize a 1-to-0 transition, the maximum count rate is 1/24 of the
oscillator frequency. To ensure that a given level is sampled at least once before it changes, the
level should be held for at least one full machine cycle.
http://www.atmel.com/dyn/resources/prod_documents/DOC4316.PDF
http://www.atmel.com/dyn/resources/prod_documents/DOC4316.PDF
RCLK +TCLK
X
0
0
1
Timer 2 Operating Modes
CP/RL2
X
X
0
1
TR2
1
1
1
0
Table
MODE
16-bit Auto-reload
16-bit Capture
Baud Rate Generator
(Off)
5-2. Timer 2 consists of two 8-bit
Table
5-2). Timer 2 has
2601C–MICRO–06/08