AT89LS52-16PC Atmel, AT89LS52-16PC Datasheet - Page 18

• Manufacturer Part Number: AT89LS52-16PC
• Description: IC MCU 8K FLASH LV 16MHZ 40-DIP
• Manufacturer: Atmel
• Series: 89LSr

Specifications of AT89LS52-16PC

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: UART/USART
• Peripherals: WDT
• Number Of I /o: 32
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 4 V
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 40-DIP (0.600", 15.24mm)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Data Converters: -

13. Interrupts
18
AT89LS52
The AT89LS52 has a total of six interrupt vectors: two external interrupts (INT0 and INT1), three
timer interrupts (Timers 0, 1, and 2), and the serial port interrupt. These interrupts are all shown
in
Each of these interrupt sources can be individually enabled or disabled by setting or clearing a
bit in Special Function Register IE. IE also contains a global disable bit, EA, which disables all
interrupts at once.
Note that
write 1 to this bit position, since it may be used in future AT89 products.
Timer 2 interrupt is generated by the logical OR of bits TF2 and EXF2 in register T2CON. Nei-
ther of these flags is cleared by hardware when the service routine is vectored to. In fact, the
service routine may have to determine whether it was TF2 or EXF2 that generated the interrupt,
and that bit will have to be cleared in software.
The Timer 0 and Timer 1 flags, TF0 and TF1, are set at S5P2 of the cycle in which the timers
overflow. The values are then polled by the circuitry in the next cycle. However, the Timer 2 flag,
TF2, is set at S2P2 and is polled in the same cycle in which the timer overflows.
Table 13-1.
Symbol
EA
–
ET2
ES
ET1
EX1
ET0
EX0
User software should never write 1s to reserved bits, because they may be used in future AT89 products.
Figure
(MSB)
Enable Bit = 1 enables the interrupt.
Enable Bit = 0 disables the interrupt.
EA
13-1.
Table 13-1
Interrupt Enable (IE) Register
–
shows that bit position IE.6 is unimplemented. User software should not
IE.2
IE.0
Position
IE.7
IE.6
IE.5
IE.4
IE.3
IE.1
ET2
ES
Function
Disables all interrupts. If EA = 0, no interrupt is
acknowledged. If EA = 1, each interrupt source is
individually enabled or disabled by setting or clearing its
enable bit.
Reserved.
Timer 2 interrupt enable bit.
Serial Port interrupt enable bit.
Timer 1 interrupt enable bit.
External interrupt 1 enable bit.
Timer 0 interrupt enable bit.
External interrupt 0 enable bit.
ET1
(LSB)
EX1
ET0
2601C–MICRO–06/08
EX0