PIC18F4431-E/ML Microchip Technology, PIC18F4431-E/ML Datasheet
PIC18F4431-E/ML
Specifications of PIC18F4431-E/ML
Related parts for PIC18F4431-E/ML
PIC18F4431-E/ML Summary of contents
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... Flash Microcontroller Programming Specification 1.0 DEVICE OVERVIEW This document includes the programming specifications for the following devices: • PIC18F2331 • PIC18F2431 • PIC18F4331 • PIC18F4431 2.0 PROGRAMMING OVERVIEW OF THE PIC18FXX31 PIC18FXX31 devices can be programmed using either the high voltage In-Circuit Serial Programming (ICSP TM ) method, or the low voltage ICSP method. Both of these can be done with the device in the users’ ...
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... DS30500B-page 2 • RB7/KBI3/PGD RB6/KBI2/PGC (1) RB5/KBI1/PWM4/PGM RB4/KBI0/PWM5 RB3/PWM3 RB2/PWM2 RB1/PWM1 RB0/PWM0 RC7/RX/DT/SDO RC6/TX/CK/SS RC5/INT2/SCK/SCL RC4/INT1/SDI/SDA RB7/KBI3/PGD RB6/KBI2/PGC (2) RB5/KBI1/PWM4/PGM RB4/KBI0/PWM5 RB3/PWM3 RB2/PWM2 RB1/PWM1 RB0/PWM0 RD7/PWM7 RD6/PWM6 (4) RD5/PWM4 (3) RD4/FLTA (1) RC7/RX/DT/SDO RC6/TX/CK/SS (1) (1) RC5/INT2/SCK /SCL (1) (1) RC4/INT1/SDI /SDA RD3/SCK/SCL RD2/SDI/SDA 2010 Microchip Technology Inc. ...
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... SCK/SCL. 2: Low voltage programming must be enabled. 3: RD4 is the alternate pin for FLTA. 4: RD5 is the alternate pin for PWM4. 2010 Microchip Technology Inc. PIC18F2331/2431/4331/4431 RC0/T1OSO/T1CKI 2 OSC2/CLKO/RA6 31 3 OSC1/CLKI/RA7 30 4 PIC18F4331 PIC18F4431 RE2/AN8 27 7 RE1/AN7 26 8 RE0/AN6 9 25 RA5/AN5/LVDIN RA4/AN4/CAP3/QEB DS30500B-page 3 ...
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... RC3 is the alternate pin for T0CKI/T5CKI, RC4 is the alternate pin for SDI/SDA, RC5 is the alternate pin for SCK/SCL. 2: Low voltage programming must be enabled. 3: RD4 is the alternate pin for FLTA. 4: RD5 is the alternate pin for PWM4. DS30500B-page 4 33 OSC2/CLKO/RA6 1 32 OSC1/CLKI/RA7 PIC18F4331 PIC18F4431 RE2/AN8 27 7 RE1/AN7 26 8 RE0/AN6 9 25 RA5/AN5/LVDIN RA4/AN4/CAP3/QEB 11 SS 2010 Microchip Technology Inc. ...
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... Configuration and ID Space 3FFFFFh Note: Sizes of memory areas not to scale. 2010 Microchip Technology Inc. PIC18F2331/2431/4331/4431 TABLE 2-2: Device PIC18F2331 PIC18F4331 PIC18F2431 PIC18F4431 MEMORY SIZE/DEVICE 8 Kbytes 16 Kbytes Address (PIC18FX331) (PIC18FX431) Range 0000h Boot Block Boot Block 0FFFh 0200h Block 0 Block 0 ...
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... ID Location 8 CONFIG1L CONFIG1H CONFIG2L CONFIG2H CONFIG3L CONFIG3H CONFIG4L CONFIG4H CONFIG5L CONFIG5H CONFIG6L CONFIG6H CONFIG7L CONFIG7H Device ID1 Device ID2 2010 Microchip Technology Inc. TBLPTRL Addr[7:0] 200000h 200001h 200002h 200003h 200004h 200005h 200006h 200007h 300000h 300001h 300002h 300003h 300004h 300005h 300006h ...
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... Verify mode places all unused I/Os in the high impedance state. FIGURE 2-6: ENTERING HIGH VOLTAGE PROGRAM/ VERIFY MODE P13 P12 P1 D110 MCLR SDATA SCLK SDATA = Input 2010 Microchip Technology Inc. PIC18F2331/2431/4331/4431 FIGURE 2-7: accessed and FIGURE 2-8: MCLR PGM SDATA SCLK HIGH LEVEL PROGRAMMING FLOW Start ...
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... Data Payload SDATA = Input COMMANDS FOR PROGRAMMING 4-Bit Description Command 0000 0010 1000 1001 1010 1011 1100 1101 1110 1111 SAMPLE COMMAND SEQUENCE Data Core Instruction Payload 3C 40 Table Write, post-increment P5A Fetch Next 4-bit Command 2010 Microchip Technology Inc. ...
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... FIGURE 3-2: BULK ERASE TIMING SCLK SDATA 4-bit Command 16-bit Data Payload 2010 Microchip Technology Inc. PIC18F2331/2431/4331/4431 TABLE 3-2: 4-Bit Command 0000 0000 0000 0000 0000 0000 1100 0000 Data 0000 80h 81h 83h FIGURE 3-1: 88h 89h 8Ah 8Bh ...
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... Programming” command, and parameters P9 and P10 is shown in Figure 3-6. Note: The TBLPTR register must contain the same offset value when initiating the pro- gramming sequence as it did when the write buffers were loaded. 2010 Microchip Technology Inc. ...
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... Step 5: Repeat step 4, with Address Pointer incremented by 64 until all panels are erased. FIGURE 3-3: MULTI-PANEL SINGLE ROW ERASE CODE MEMORY FLOW Addr = Addr + 64 2010 Microchip Technology Inc. PIC18F2331/2431/4331/4431 Core Instruction BSF EECON1, EEPGD BSF EECON1, CFGS ...
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... The TBLPTR register must contain the same offset value when initiating the pro- gramming sequence as it did when the write buffers were loaded. Offset = TBLPTR<12:3> Offset = TBLPTR<12:3> Erase Region (64 bytes) Offset = TBLPTR<12:6> Erase Region (64 bytes) Offset = TBLPTR<12:6> 2010 Microchip Technology Inc. ...
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... To continue writing data, repeat steps 2 through 5, where the Address Pointer is incremented each panel at each iteration of the loop. 2010 Microchip Technology Inc. PIC18F2331/2431/4331/4431 Core Instruction BSF EECON1, EEPGD BSF EECON1, CFGS BSF EECON1, WREN ...
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... All No Panel Buffers Written? Yes Start Write Sequence and Hold SCLK High until Done Delay P9+P10 Time for Write to Occur All No Locations Done? Yes Done P5A 4-bit Command SDATA = Input P10 16-bit Programming Time Data Payload 2010 Microchip Technology Inc. ...
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... In this case, however assumed that the address space to be written already has data in it (i.e not blank). 2010 Microchip Technology Inc. PIC18F2331/2431/4331/4431 The minimum amount of code memory that may be erased at a given time is 64 bytes. Again, the device must be placed in Single Panel Write mode ...
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... MOVLW <Addr[8:15]> MOVWF TBLPTRH MOVLW <Addr[7:0]> MOVWF TBLPTRL Write 2 bytes and post-increment address by 2 Write 2 bytes and post-increment address by 2 Write 2 bytes and post-increment address by 2 Write 2 bytes and start programming NOP - hold SCLK high for time P9 2010 Microchip Technology Inc. ...
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... SCLK P5 SDATA BSF EECON1, WR 4-bit Command SCLK Poll WR bit SDATA 4-bit Command 2010 Microchip Technology Inc. PIC18F2331/2431/4331/4431 FIGURE 3-7: P5A Poll WR bit, Repeat until Clear (see below) SDATA = Input P5A MOVWF TABLAT 4-bit Command MOVF EECON1 SDATA = Input PROGRAM DATA FLOW ...
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... BCF EECON1, CFGS MOVLW <Addr> MOVWF EEADR MOVLW <AddrH> MOVWF EEADRH MOVLW <Data> MOVWF EEDATA BSF EECON1, WREN MOVLW 0X55 MOVWF EECON2 MOVLW 0XAA MOVWF EECON2 BSF EECON1, WR MOVF EECON1 MOVWF TABLAT (1) Shift out data BCF EECON1, WREN 2010 Microchip Technology Inc. ...
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... In order to modify the ID locations, refer to the method- ology described in Section 3.2.2, “Modifying Code Memory”. As with code memory, the ID locations must be erased before modified. 2010 Microchip Technology Inc. PIC18F2331/2431/4331/4431 Note: Even though multi-panel writes are dis- abled, the user must still fill the 8-byte data buffer for the panel ...
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... Load 2 bytes and start programming NOP - hold SCLK high for time P9 INCF TBLPTRL Load 2 bytes and start programming NOP - hold SCLK high for time P9 Load Odd Configuration Address Program Delay P9 Time for Write Start MSB Done 2010 Microchip Technology Inc. ...
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... SDATA SDATA = Input 2010 Microchip Technology Inc. PIC18F2331/2431/4331/4431 The 4-bit command is shifted in LSb first. The table read is executed during the next 8 clocks, then shifted out on SDATA during the last 8 clocks, LSb to MSb. A delay of P6 must be introduced after the falling edge of the 8th SCLK of the operand to allow SDATA to transi- tion from an input to an output ...
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... Set Pointer = 200000h Read Low Byte Read High byte No Failure, Word = Expect Report Error No Does No Failure, Data? Report Error Yes All ID Locations Verified? Yes Done 2010 Microchip Technology Inc. ...
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... SCLK of the operand to allow SDATA to transition from an input to an output. During this time, SCLK must be held low (see Figure 4-4). The command sequence to read a single byte of data is shown in Table 4-2. 2010 Microchip Technology Inc. PIC18F2331/2431/4331/4431 FIGURE 4-3: No READ DATA EEPROM ...
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... BCF EECON1, CFGS MOVLW <Addr> MOVWF EEADR MOVLW <AddrH> MOVWF EEADRH BSF EECON1, RD MOVF EEDATA MOVWF TABLAT (1) Shift Out Data P14 LSb Shift Data Out SDATA = Output P5A 5 6 MSb Fetch Next 4-bit Command SDATA = Input 2010 Microchip Technology Inc. ...
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... Unused (reserved) configuration bits will read ‘0’ (pro- grammed). Refer to Table 5-2 and Table 5-3 for blank configuration expect data for the various PIC18FXX31 devices. 2010 Microchip Technology Inc. PIC18F2331/2431/4331/4431 Given that “Blank Checking” is merely code and data EEPROM verification with FFh expect data, refer to Section 4 ...
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... TABLE 5-1: DEVICE ID VALUES Device PIC18F2331 PIC18F2431 PIC18F4331 PIC18F4431 Note: The ‘x’s in DEVID1 contain the device revision code. DS30500B-page 26 5.3 Low Voltage Programming (LVP) Bit The LVP bit in Configuration register, CONFIG4L, enables low voltage ICSP programming. The LVP bit defaults to a ‘ ...
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... CONFIG7H — EBTRB 3FFFFEh DEVID1 DEV2 DEV1 3FFFFFh DEVID2 DEV10 DEV9 Legend unknown unchanged unimplemented value depends on condition. Shaded cells are unimplemented, read as ‘0’. 2010 Microchip Technology Inc. PIC18F2331/2431/4331/4431 Bit 5 Bit 4 Bit 3 Bit 2 — — OSC OSC — ...
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... HPOL and LPOL. 4: This bit is reserved on PIC18F2X31 devices and should be maintained set (i.e., equal to ‘1’). 5: For PIC18FX431 devices only. DS30500B-page 28 Description set to 2.0V BOR set to 2.7V BOR set to 4.2V BOR set to 4.5V BOR 1) OSC 2010 Microchip Technology Inc. ...
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... HPOL and LPOL. 4: This bit is reserved on PIC18F2X31 devices and should be maintained set (i.e., equal to ‘1’). 5: For PIC18FX431 devices only. 2010 Microchip Technology Inc. PIC18F2331/2431/4331/4431 Description can enable the special event trigger signal from IC1 to reset the TMR5 time base. ...
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... HPOL and LPOL. 4: This bit is reserved on PIC18F2X31 devices and should be maintained set (i.e., equal to ‘1’). 5: For PIC18FX431 devices only. DS30500B-page 30 Description respectively. SDO output is multiplexed with RC7. respectively. SDO output is multiplexed with RD1. communication function) 2010 Microchip Technology Inc. ...
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... PWMEN<2:0> = 100 if the device has six PWM output pins (28-pin device). PWM output polarity is defined by HPOL and LPOL. 4: This bit is reserved on PIC18F2X31 devices and should be maintained set (i.e., equal to ‘1’). 5: For PIC18FX431 devices only. 2010 Microchip Technology Inc. PIC18F2331/2431/4331/4431 Description (1) DS30500B-page 31 ...
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... HPOL and LPOL. 4: This bit is reserved on PIC18F2X31 devices and should be maintained set (i.e., equal to ‘1’). 5: For PIC18FX431 devices only. DS30500B-page 32 Description other blocks blocks other blocks blocks other blocks blocks other blocks blocks other blocks other blocks 2010 Microchip Technology Inc. ...
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... An option to not include the configuration word information may be provided. When embedding configuration word information in the HEX file, it should start at address 300000h. Microchip Technology Inc. feels strongly that this feature is important for the benefit of the end customer. 2010 Microchip Technology Inc. PIC18F2331/2431/4331/4431 5 ...
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... Description CFGW = Configuration Word SUM[a:b] = Sum of locations inclusive SUM_ID = Byte-wise sum of lower four bits of all customer ID locations + = Addition & = Bit-wise AND DS30500B-page 34 Checksum 2010 Microchip Technology Inc. 0xAA at 0 Blank and Max Value Address E464 E3BA E640 E5F5 043D 0447 ...
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... Legend: Item Description CFGW = Configuration Word SUM[a:b] = Sum of locations inclusive SUM_ID = Byte-wise sum of lower four bits of all customer ID locations + = Addition & = Bit-wise AND 2010 Microchip Technology Inc. PIC18F2331/2431/4331/4431 Checksum 0xAA at 0 Blank and Max Value Address C488 C3DE C668 ...
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... Description CFGW = Configuration Word SUM[a:b] = Sum of locations inclusive SUM_ID = Byte-wise sum of lower four bits of all customer ID locations + = Addition & = Bit-wise AND DS30500B-page 36 Checksum 2010 Microchip Technology Inc. 0xAA at 0 Blank and Max Value Address E3A4 E2FA E5C3 E578 03C0 03CA ...
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... PIC18F4431 SUM(IDs) Boot SUM(2000:2FFF)+SUM(3000:3FFF)+(CONFIG0 & 0000)+ Block/ (CONFIG1 & ...
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... PP 10 — ns s 2 — PP 2010 Microchip Technology Inc. Conditions Normal programming V Bulk erase operations 8 -3 meet AC specifications 2.0V DD ...
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... REAL ICE, rfLAB, Select Mode, Total Endurance, TSHARC, UniWinDriver, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. ...
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