PIC18F4431-E/ML Microchip Technology, PIC18F4431-E/ML Datasheet - Page 12

• Manufacturer Part Number: PIC18F4431-E/ML
• Description: IC MCU FLASH 8KX16 44QFN
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F4431-E/ML

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, Power Control PWM, QEI, POR, PWM, WDT
• Number Of I /o: 36
• Program Memory Size: 16KB (8K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 768 x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 9x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 44-QFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

PIC18F2331/2431/4331/4431
3.2
Programming code memory is accomplished by first
loading data into the appropriate write buffers and then
initiating a programming sequence. Each panel in the
code memory space (see Figure 2-4) has an 8-byte
deep write buffer that must be loaded prior to initiating
a write sequence. The actual memory write sequence
takes the contents of these buffers and programs the
associated EEPROM code memory.
Typically, all of the program buffers are written in paral-
lel (Multi-Panel Write mode). In other words, in the case
of a 16-Kbyte device (2 panels with an 8-byte buffer per
panel), 16 bytes will be simultaneously programmed
during each programming sequence. In this case, the
offset of the write within each panel is the same (see
Figure 3-4). Multi-Panel Write mode is enabled by
appropriately configuring the Programming Control
register located at 3C0006h.
FIGURE 3-4:
DS30500B-page 12
Note: TBLPTR = TBLPTRU:TBLPTRH:TBLPTRL.
Panel 2
TBLPTR<21:13> = 1
Panel 1
TBLPTR<21:13> = 0
Code Memory Programming
TBLPTR<2:0> = 7
TBLPTR<2:0> = 6
TBLPTR<2:0> = 5
TBLPTR<2:0> = 4
TBLPTR<2:0> = 3
TBLPTR<2:0> = 2
TBLPTR<2:0> = 1
TBLPTR<2:0> = 0
TBLPTR<2:0> = 7
TBLPTR<2:0> = 6
TBLPTR<2:0> = 5
TBLPTR<2:0> = 4
TBLPTR<2:0> = 3
TBLPTR<2:0> = 2
TBLPTR<2:0> = 1
TBLPTR<2:0> = 0
ERASE AND WRITE BOUNDARIES
Offset = TBLPTR<12:3>
Offset = TBLPTR<12:3>
The programming duration is externally timed and is
controlled by SCLK. After a “Start Programming” com-
mand is issued (4-bit command, ‘1111’), a NOP is
issued, where the 4th SCLK is held high for the
duration of the programming time, P9.
After SCLK is brought low, the programming sequence
is terminated. SCLK must be held low for the time spec-
ified by parameter P10 to allow high voltage discharge
of the memory array.
The code sequence to program a PIC18FXX31 device
is shown in Table 3-4. The flowchart shown in
Figure 3-5 depicts the logic necessary to completely
write a PIC18FXX31 device. The timing diagram that
details the “Start Programming” command, and
parameters P9 and P10, is shown in Figure 3-6.
Note:
The TBLPTR register must contain the
same offset value when initiating the pro-
gramming sequence as it did when the
write buffers were loaded.
 2010 Microchip Technology Inc.
Erase Region
Erase Region
Offset = TBLPTR<12:6>
Offset = TBLPTR<12:6>
(64 bytes)
(64 bytes)