PIC18F4431-E/ML Microchip Technology, PIC18F4431-E/ML Datasheet
PIC18F4431-E/ML
Specifications of PIC18F4431-E/ML
Related parts for PIC18F4431-E/ML
PIC18F4431-E/ML Summary of contents
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... PIC18F2331/2431/4331/4431 Microcontrollers with nanoWatt Technology, High-Performance PWM and A/D 2010 Microchip Technology Inc. Data Sheet 28/40/44-Pin Enhanced Flash DS39616D ...
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... PICtail, REAL ICE, rfLAB, Select Mode, Total Endurance, TSHARC, UniWinDriver, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. ...
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... PIC18F2431 16384 8192 768 PIC18F4331 8192 4096 768 PIC18F4431 16384 8192 768 2010 Microchip Technology Inc. PIC18F2331/2431/4331/4431 Power-Managed Modes: • Run: CPU on, Peripherals on • Idle: CPU off, Peripherals on • Sleep: CPU off, Peripherals off • Ultra Low Input Leakage • ...
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... For the QFN package recommended that the bottom pad be connected to V Note 1: DS39616D-page -/CAP1/INDX 1 21 REF +/CAP2/QEA 2 20 REF 3 19 PIC18F2331 PIC18F2431 OSC1/CLKI/RA7 RB7/KBI3/PGD RB6/KBI2/PGC RB5/KBI1/PWM4/PGM RB4/KBI0/PWM5 RB3/PWM3 RB2/PWM2 RB1/PWM1 RB0/PWM0 RC7/RX/DT/SDO RC6/TX/CK/SS RC5/INT2/SCK/SCL RC4/INT1/SDI/SDA RB3/PWM3 RB2/PWM2 RB1/PWM1 RB0/PWM0 RC7/RX/DT/SDO . SS 2010 Microchip Technology Inc. ...
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... RD0/T0CKI/T5CKI RD1/SDO Note 1: RC3 is the alternate pin for T0CKI/T5CKI; RC4 is the alternate pin for SDI/SDA; RC5 is the alternate pin for SCK/SCL. 2: RD4 is the alternate pin for FLTA. 3: RD5 is the alternate pin for PWM4. 2010 Microchip Technology Inc. PIC18F2331/2431/4331/4431 ...
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... Note 1: RC3 is the alternate pin for T0CKI/T5CKI; RC4 is the alternate pin for SDI/SDA; RC5 is the alternate pin for SCK/SCL. 2: RD4 is the alternate pin for FLTA. 3: RD5 is the alternate pin for PWM4. DS39616D-page RC0/T1OSO/T1CKI OSC2/CLKO/RA6 3 30 OSC1/CLKI/RA7 PIC18F4331 PIC18F4431 27 RE2/AN8 7 RE1/AN7 8 26 RE0/AN6 9 25 RA5/AN5/LVDIN RA4/AN4/CAP3/QEB 2010 Microchip Technology Inc. ...
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... For the QFN package recommended that the bottom pad be connected RD4 is the alternate pin for FLTA. 4: RD5 is the alternate pin for PWM4. 2010 Microchip Technology Inc. PIC18F2331/2431/4331/4431 OSC2/CLKO/RA6 1 33 OSC1/CLKI/RA7 PIC18F4331 PIC18F4431 7 27 RE2/AN8 8 RE1/AN7 26 9 RE0/AN6 25 RA5/AN5/LVDIN RA4/AN4/CAP3/QEB DS39616D-page 7 ...
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... Appendix E: Migration From Mid-Range to Enhanced Devices ......................................................................................................... 377 Appendix F: Migration From High-End to Enhanced Devices............................................................................................................ 377 INDEX ................................................................................................................................................................................................ 379 The Microchip Web Site ..................................................................................................................................................................... 389 Customer Change Notification Service .............................................................................................................................................. 389 Customer Support .............................................................................................................................................................................. 389 Reader Response .............................................................................................................................................................................. 390 Product Identification System............................................................................................................................................................. 391 DS39616D-page 8 2010 Microchip Technology Inc. ...
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... When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are using. Customer Notification System Register on our web site at www.microchip.com to receive the most current information on all of our products. 2010 Microchip Technology Inc. PIC18F2331/2431/4331/4431 DS39616D-page 9 ...
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... PIC18F2331/2431/4331/4431 NOTES: DS39616D-page 10 2010 Microchip Technology Inc. ...
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... This document contains device-specific information for the following devices: • PIC18F2331 • PIC18LF2331 • PIC18F2431 • PIC18LF2431 • PIC18F4331 • PIC18LF4331 • PIC18F4431 • PIC18LF4431 This family offers the advantages of all PIC18 microcontrollers – namely, high performance at an economical price, with the addition of high-endurance enhanced Flash program memory and a high-speed 10-bit A/D Converter ...
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... Timer5 as the time base, a Special Event Trigger to other modules and an adjustable noise filter on each IC input. • Extended Watchdog Timer (WDT): This enhanced version incorporates a 16-bit prescaler, allowing a time-out range from over 2 minutes, that is stable across operating voltage and temperature. for 2010 Microchip Technology Inc. ...
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... Yes 75 Instructions 75 Instructions 28-pin SPDIP 28-pin SPDIP 28-pin SOIC 28-pin SOIC 28-pin QFN 28-pin QFN Table 1-1. Table 1-2 and range of 4.2V to 5.5V. DD range DD PIC18F4331 PIC18F4431 DC – 40 MHz DC – 40 MHz 8192 16384 4096 8192 768 768 256 256 34 34 Ports Ports ...
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... PORTA RA0/AN0 RA1/AN1 RA2/AN2/V -/CAP1/INDX REF RA3/AN3/V +/CAP2/QEA REF RA4/AN4/CAP3/QEB OSC2/CLKO/RA6 OSC1/CLKI/RA7 PORTB RB0/PWM0 RB1/PWM1 RB2/PWM2 RB3/PWM3 RB4/KBI0/PWM5 RB5/KBI1/PWM4/PGM RB6/KBI2/PGC RB7/KBI3/PGD PORTC RC0/T1OSO/T1CKI RC1/T1OSI/CCP2/FLTA RC2/CCP1 RC3/T0CKI/T5CKI/INT0 RC4/INT1/SDI/SDA RC5/INT2/SCK/SCL RC6/TX/CK/SS RC7/RX/DT/SDO 8 PORTE MCLR 10-Bit ADC PCPWM MFM 2010 Microchip Technology Inc. ...
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... RE3 is available only when MCLR is disabled. Note 1: RD4 is the alternate pin for FLTA. 2: RC3, RC4 and RC5 are alternate pins for T0CKI/T5CKI, SDI/SDA, SCK/SCL, respectively. 3: RD5 is the alternate pin for PWM4. 4: 2010 Microchip Technology Inc. PIC18F2331/2431/4331/4431 Data Bus<8> Data Latch 8 8 Data RAM (768 bytes) ...
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... A/D reference voltage (high) input Input Capture Pin Quadrature Encoder Interface Channel A input pin. 3 I/O TTL Digital I/O. I Analog Analog Input Input Capture Pin Quadrature Encoder Interface Channel B input pin. CMOS = CMOS compatible input or output I = Input P = Power Description 2010 Microchip Technology Inc. ...
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... RB7 KBI3 PGD Legend: TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels O = Output 2010 Microchip Technology Inc. PIC18F2331/2431/4331/4431 Pin Buffer Type Type QFN PORTB is a bidirectional I/O port. PORTB can be software programmed for internal weak pull-ups on all inputs. ...
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... EUSART synchronous data (see related TX/CK). O — SPI data out — Ground reference for logic and I/O pins — Positive supply for logic and I/O pins. CMOS = CMOS compatible input or output I = Input P = Power Description 2 C mode. 2010 Microchip Technology Inc. ...
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... RC3 is the alternate pin for T0CKI/T5CKI; RC4 is the alternate pin for SDI/SDA; RC5 is the alternate pin Note 1: for SCK/SCL; RC7 is the alternate pin for SDO. RD4 is the alternate pin for FLTA. 2: RD5 is the alternate pin for PWM4. 3: 2010 Microchip Technology Inc. PIC18F2331/2431/4331/4431 Pin Buffer Type Type 18 Master Clear (input) or programming voltage (input) ...
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... I/O TTL Digital I/O. I Analog Analog Input Input Capture Pin Quadrature Encoder Interface Channel B input pin. 24 I/O TTL Digital I/O. I Analog Analog Input 5. I Analog Low-Voltage Detect input. CMOS = CMOS compatible input or output I = Input P = Power Description 2010 Microchip Technology Inc. ...
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... RC3 is the alternate pin for T0CKI/T5CKI; RC4 is the alternate pin for SDI/SDA; RC5 is the alternate pin Note 1: for SCK/SCL; RC7 is the alternate pin for SDO. RD4 is the alternate pin for FLTA. 2: RD5 is the alternate pin for PWM4. 3: 2010 Microchip Technology Inc. PIC18F2331/2431/4331/4431 Pin Buffer Type Type PORTB is a bidirectional I/O port. PORTB can be software programmed for internal weak pull-ups on all inputs ...
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... EUSART synchronous clock (see related RX/DT SPI slave select input. 1 I/O ST Digital I/ EUSART asynchronous receive. I/O ST EUSART synchronous data (see related TX/CK). O — SPI data out. CMOS = CMOS compatible input or output I = Input P = Power Description 2 C mode. 2010 Microchip Technology Inc. ...
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... RC3 is the alternate pin for T0CKI/T5CKI; RC4 is the alternate pin for SDI/SDA; RC5 is the alternate pin Note 1: for SCK/SCL; RC7 is the alternate pin for SDO. RD4 is the alternate pin for FLTA. 2: RD5 is the alternate pin for PWM4. 3: 2010 Microchip Technology Inc. PIC18F2331/2431/4331/4431 Pin Buffer Type Type PORTD is a bidirectional I/O port. ...
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... Analog Analog Input 7. 27 I/O ST Digital I/O. I Analog Analog Input 8. P — Ground reference for logic and I/O pins — Positive supply for logic and I/O pins connect. CMOS = CMOS compatible input or output I = Input P = Power Description 2010 Microchip Technology Inc. ...
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... REF REF reference for analog modules is implemented The AV and AV pins must always be Note connected, regardless of whether any of the analog modules are being used. The minimum mandatory connections are shown in Figure 2-1. 2010 Microchip Technology Inc. PIC18F2331/2431/4331/4431 FIGURE 2- MCLR ( Pin” ...
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... V DD Not all devices incorporate software BOR Note: control. See device-specific information. may result in a spontaneous DD does not approach the set point. DD and circuit as the microcontroller for Section 5.0 “Reset” 2010 Microchip Technology Inc. ...
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... Electrostatic Discharge (ESD) or Electrical Overstress (EOS). Ensure that the MCLR pin V and V specifications are met 2010 Microchip Technology Inc. PIC18F2331/2431/4331/4431 2.4 ICSP Pins device The PGC and PGD pins are used for In-Circuit Serial Programming™ (ICSP™) and debugging purposes. It ...
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... Bottom Layer Copper Pour (tied to ground) OSCO GND Devices” OSCI DEVICE PINS SUGGESTED PLACEMENT OF THE OSCILLATOR CIRCUIT Primary Oscillator Crystal DEVICE PINS OSC1 ` OSC2 GND ` T1OSO T1OS Oscillator: C2 Top Layer Copper Pour (tied to ground) C2 Oscillator Crystal C1 2010 Microchip Technology Inc. ...
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... The oscillator design requires the use of a parallel resonant crystal. Use of a series resonant crystal may give Note: a frequency out of manufacturers’ specifications. 2010 Microchip Technology Inc. PIC18F2331/2431/4331/4431 FIGURE 3-1: (1) C1 (1) C2 Note 1: See C1 and C2 series resistor (R strip resonant crystals ...
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... Configuration Register 1H) OSC2 HS Mode Crystal OSC1 Osc of external Figure 3-2. EXTERNAL CLOCK INPUT OPERATION (HS OSC CONFIGURATION) OSC1 PIC18FXXXX (HS Mode) OSC2 Open PLL BLOCK DIAGRAM HS Osc Enable PLL Enable Phase F IN Comparator F OUT Loop Filter 4 VCO SYSCLK 2010 Microchip Technology Inc. ...
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... CONFIGURATION) OSC1/CLKI Clock from Ext. System PIC18FXXXX RA6 I/O (OSC2) 2010 Microchip Technology Inc. PIC18F2331/2431/4331/4431 3.5 RC Oscillator For timing-insensitive applications, the “RC” and “RCIO” device options offer additional cost savings. The actual oscillator frequency is a function of several factors: • ...
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... Three compensation techniques are discussed in Section 3.6.4.1 EUSART”, Section 3.6.4.2 “Compensating with the and Timers” Section 3.6.4.3 “Compensating with the CCP Module in Capture may be used. or temperature changes, which can DD “Compensating with the Mode”, but other techniques 2010 Microchip Technology Inc. ...
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... If the internally clocked timer value is greater than expected, the internal oscillator block is running too fast. To adjust for this, decrement the OSCTUNE register. 2010 Microchip Technology Inc. PIC18F2331/2431/4331/4431 R/W-0 R/W-0 R/W-0 ...
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... It is recommended that the Timer1 oscillator be operating and stable before executing the SLEEP instruction very long delay may occur while the Timer1 oscillator starts. (Register 3-2) controls sev- Section 4.0 when executing a SLEEP 2010 Microchip Technology Inc. ...
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... Sleep OSC1 Secondary Oscillator T1OSO T1OSCEN Enable Oscillator T1OSI OSCCON<6:4> Internal Oscillator Block INTRC Source 2010 Microchip Technology Inc. PIC18F2331/2431/4331/4431 CONFIG1H <3:0> HSPLL 4 x PLL LP, XT, HS, RC, EC Clock Source Option for other Modules OSCCON<6:4> 8 MHz 111 4 MHz 110 2 MHz 101 ...
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... Depends on the state of the IESO bit in Configuration Register 1H. Note 1: Default output frequency of INTOSC on Reset. 2: DS39616D-page 36 (1) R/W-0 R R-0 IRCF0 OSTS IOFS U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (2) (1) R/W-0 R/W-0 SCS1 SCS0 bit Bit is unknown 2010 Microchip Technology Inc. ...
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... See Table 5-1 in Note: Section 5.0 “Reset” 2010 Microchip Technology Inc. PIC18F2331/2431/4331/4431 directly to clock the system, or may be divided down first. The INTOSC output is disabled if the system clock is provided directly from the INTRC output. If the Sleep mode is selected, all clock sources are stopped ...
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... PIC18F2331/2431/4331/4431 NOTES: DS39616D-page 38 2010 Microchip Technology Inc. ...
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... IDLEN reflects its value when the SLEEP instruction is executed. Note 1: Includes INTOSC and INTOSC postscaler, as well as the INTRC source. 2: 2010 Microchip Technology Inc. PIC18F2331/2431/4331/4431 4.1.1 CLOCK SOURCES The SCS<1:0> bits allow the selection of one of three clock sources for power-managed modes. They are: • ...
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... OSTS bit is set and the primary clock is providing the clock. The IDLEN and SCS bits are not affected by the wake-up; the Timer1 oscillator continues to run. 2010 Microchip Technology Inc. Section 3.7.1 “Oscillator 4-1), the primary oscillator Figure 4-2). ...
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... PRI_RUN and RC_RUN modes during execution. However, a clock switch delay will occur during entry to and exit from RC_RUN mode. Therefore, if the primary clock source is the internal oscillator block, the use of RC_RUN mode is not recommended. 2010 Microchip Technology Inc. PIC18F2331/2431/4331/4431 n-1 ...
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... The INTRC source will continue to run if either the WDT or the Fail-Safe Clock Monitor is enabled n-1 n (1) Clock Transition OSC (1) OST PLL ( n-1 n Clock (2) Transition PC OSTS bit Set = 2 ms (approx). These intervals are not shown to scale. PLL . OSC Figure 4-4). When the clock 2010 Microchip Technology Inc. ...
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... (approx). These intervals are not shown to scale. OST OSC PLL 2010 Microchip Technology Inc. PIC18F2331/2431/4331/4431 4.4 Idle Modes The Idle modes allow the controller’s CPU to be selectively shut down while the peripherals continue to operate. Selecting a particular Idle mode allows users to further manage power consumption. If the IDLEN bit is set to a ‘ ...
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... CSD the Timer1 oscillator is enabled but not yet running, peripheral clocks will be delayed until the oscillator has started. In such situations, initial oscillator operation is far from stable and unpredictable operation 4-8). may result CSD PC Figure 4-8 2010 Microchip Technology Inc. ...
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... INTCON or PIE registers. The exit sequence is initiated when the corresponding interrupt flag bit is set. 2010 Microchip Technology Inc. PIC18F2331/2431/4331/4431 On all exits from Idle or Sleep modes by interrupt, code execution branches to the interrupt vector if the GIE/ GIEH bit (INTCON< ...
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... CSD (2) INTOSC T IOBST Section 4.4 “Idle Modes”). is the PLL Lock-out Timer (Parameter F12 (Parameter 39), the INTOSC stabilization period. IOBST Clock Ready Status Bit (OSCCON) OSTS (1) IOFS (3) ( OSTS rc (1) (4) IOFS (3) ( OSTS rc (1) IOFS (3) ( OSTS rc (1) (4) IOFS 2010 Microchip Technology Inc. ...
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... INTRC 11-Bit Ripple Counter Note 1: See Table 5-1 for time-out situations. 2010 Microchip Technology Inc. PIC18F2331/2431/4331/4431 This section discusses Resets generated by MCLR, POR and BOR, and the operation of the various start- up timers. Stack Reset events are covered in Section 6.1.2.4 “Stack Full/Underflow ...
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... Power-on Reset has been Registers”. detected, so that subsequent Power-on Resets may be detected. R/W-1 R-1 R Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (2) (1) for additional information. R/W-0 R/W-0 (2) (1) POR BOR bit Bit is unknown 2010 Microchip Technology Inc. ...
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... Note: recommended F capacitor should be connected across AV and similar capacitor connected across V DD 2010 Microchip Technology Inc. PIC18F2331/2431/4331/4431 FIGURE 5- Section 11.5 Note 1: External Power-on Reset circuit is required only if the V too slow. The diode, D, helps discharge the capacitor quickly when V down. ...
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... OSC OSC + 1024 T 1024 T OSC OSC (1) — (1) — (1) — typically 2 ms and follows the PLL Figure 5-3 through Figure 5-3 through (Figure 5-5). This is Exit From Power-Managed Mode (2) (2) 1024 OSC 1024 T OSC — — — 2010 Microchip Technology Inc. ...
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... DD MCLR INTERNAL POR PWRT TIME-OUT OST TIME-OUT INTERNAL RESET 2010 Microchip Technology Inc. PIC18F2331/2431/4331/4431 Status bits from the RCON register (RI, TO, PD, POR and BOR) are set or cleared differently in different Reset situations, as indicated in are used in software to determine the nature of the Reset. ...
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... V DD MCLR INTERNAL POR PWRT TIME-OUT OST TIME-OUT INTERNAL RESET FIGURE 5-6: SLOW RISE TIME (MCLR TIED MCLR INTERNAL POR PWRT TIME-OUT OST TIME-OUT INTERNAL RESET DS39616D-page 52 T PWRT RISE > PWRT T OST ): CASE 2 DD OST ) PWRT 2010 Microchip Technology Inc. ...
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... Interrupt exit from power-managed modes u = unchanged unknown unimplemented bit, read as ‘0’. Legend: When the wake-up is due to an interrupt and the GIEH or GIEL bits are set, the PC is loaded with the Note 1: interrupt vector (0x000008h or 0x000018h). 2010 Microchip Technology Inc. PIC18F2331/2431/4331/4431 T PWRT T OST ...
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... --uu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu (1) uuuu uuuu (1) uuuu -u-u (1) uu-u u-uu N/A N/A N/A N/A N/A ---- uuuu uuuu uuuu uuuu uuuu N/A N/A N/A N/A N/A 2010 Microchip Technology Inc. ...
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... Bit 3 of PORTE and LATE are enabled if MCLR functionality is disabled. When not enabled as the PORTE 6: pin, they are disabled and read as ‘0’. The 28-pin devices do not have only RE3 implemented. 2010 Microchip Technology Inc. PIC18F2331/2431/4331/4431 MCLR Resets Power-on Reset, ...
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... Bit 3 of PORTE and LATE are enabled if MCLR functionality is disabled. When not enabled as the PORTE 6: pin, they are disabled and read as ‘0’. The 28-pin devices do not have only RE3 implemented. 2010 Microchip Technology Inc. PIC18F2331/2431/4331/4431 MCLR Resets Power-on Reset, ...
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... Bit 3 of PORTE and LATE are enabled if MCLR functionality is disabled. When not enabled as the PORTE 6: pin, they are disabled and read as ‘0’. The 28-pin devices do not have only RE3 implemented. 2010 Microchip Technology Inc. PIC18F2331/2431/4331/4431 MCLR Resets Power-on Reset, ...
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... PIC18F2331/2431/4331/4431 NOTES: DS39616D-page 60 2010 Microchip Technology Inc. ...
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... High-Priority Interrupt Vector LSb Low-Priority Interrupt Vector LSb On-Chip Flash Program Memory Unused Read ‘0’s 2010 Microchip Technology Inc. PIC18F2331/2431/4331/4431 6.1 Program Memory Organization PIC18 microcontrollers implement a 21-bit program counter that can address a 2-Mbyte program memory space. Accessing a location between the upper bound- ary of the physically implemented memory and the 2-Mbyte address will return all ‘ ...
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... The STKFUL bit will remain set and the Stack Pointer will be set to zero. If STVREN is cleared, the STKFUL bit will be set on the 31st push and the Stack Pointer will increment to 31. Any additional pushes will not overwrite the 31st push and STKPTR will remain at 31. 2010 Microchip Technology Inc. ...
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... Unimplemented: Read as ‘0’ bit 4-0 SP<4:0>: Stack Pointer Location bits Bit 7 and bit 6 are cleared by user software POR. Note 1: 2010 Microchip Technology Inc. PIC18F2331/2431/4331/4431 Returning a value of zero to the Note: underflow has the effect of vectoring the program to the Reset vector, where the stack conditions can be verified and appropriate actions can be taken ...
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... In this method, only one data byte can be stored in each instruction location and room on the return address stack is required. EXAMPLE 6-2: COMPUTED GOTO USING AN OFFSET VALUE MOVFW OFFSET CALL TABLE ORG 0xnn00 TABLE ADDWF PCL RETLW 0xnn RETLW 0xnn RETLW 0xnn . . . 2010 Microchip Technology Inc. ...
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... Instruction @ address SUB_1 All instructions are single cycle, except for any program branches. These take two cycles since the fetch instruction is “flushed” from the pipeline, while the new instruction is being fetched and then executed. 2010 Microchip Technology Inc. PIC18F2331/2431/4331/4431 6.2 ...
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... Execute this word as a NOP REG3 ; continue code REG1 ; is RAM location 0? REG1, REG2 ; Yes, execute this word ; 2nd word of instruction REG3 ; continue code Set”. Word Address 000000h 000002h 000004h 000006h 000008h 00000Ah 00000Ch 00000Eh 000010h 000012h 000014h 2010 Microchip Technology Inc. ...
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... Bank 14 00h = 1111 Bank 15 FFh 2010 Microchip Technology Inc. PIC18F2331/2431/4331/4431 The instruction set and architecture allow operations across all banks. The entire data memory may be accessed by Direct, Indirect or Indexed Addressing modes. Addressing modes are discussed later in this subsection. To ensure that commonly used registers (SFRs and select GPRs) can be accessed in a single cycle, PIC18 devices implement an Access Bank ...
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... This is data RAM, which is available for use by all instructions. GPRs start at the bottom of Bank 0 (address 000h) and grow upwards towards the bottom of the SFR area. GPRs are not initialized by a Power-on Reset and are unchanged on all other Resets. 2010 Microchip Technology Inc. ...
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... Note 1: Unimplemented registers are read as ‘0’. 2: This register is not available on 28-pin devices. 3: 2010 Microchip Technology Inc. PIC18F2331/2431/4331/4431 “core” are described in this section, while those related to the operation of the peripheral features are described in the section of that peripheral feature. The SFRs are typically distributed among the peripherals whose functions they control ...
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... N/A N/A N/A N/A N/A ---- xxxx xxxx xxxx xxxx xxxx N/A N/A N/A N/A N/A ---- 0000 xxxx xxxx ---- 0000 N/A N/A N/A N/A N/A ---- 0000 xxxx xxxx ---x xxxx 0000 0000 xxxx xxxx T0PS1 T0PS0 1111 1111 2010 Microchip Technology Inc. ...
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... These registers and/or bits are not implemented on the PIC18F2331/2431 devices and read as ‘0’. 4: The RE3 port bit is only available for PIC18F4331/4431 devices when the MCLRE fuse (CONFIG3H<7>) is programmed to ‘0’; otherwise, RE3 5: reads ‘0’. This bit is read-only. 2010 Microchip Technology Inc. PIC18F2331/2431/4331/4431 Bit 5 Bit 4 Bit 3 ...
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... RE1 RE0 ---- xxxx RD1 RD0 xxxx xxxx RC1 RC0 xxxx xxxx RB1 RB0 xxxx xxxx RA1 RA0 xx0x 0000 PTMOD1 PTMOD0 0000 0000 — — 00-- ---- 0000 0000 ---- 0000 1111 1111 ---- 1111 2010 Microchip Technology Inc. ...
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... These registers and/or bits are not implemented on the PIC18F2331/2431 devices and read as ‘0’. 4: The RE3 port bit is only available for PIC18F4331/4431 devices when the MCLRE fuse (CONFIG3H<7>) is programmed to ‘0’; otherwise, RE3 5: reads ‘0’. This bit is read-only. 2010 Microchip Technology Inc. PIC18F2331/2431/4331/4431 Bit 5 Bit 4 Bit 3 ...
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... For other instructions not affecting any Status bits, see Table 24-2. The C and DC bits operate as a Borrow Note: and Digit Borrow bit respectively, in subtraction. R/W-x R/W-x R/W Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) R/W-x R/W-x (1) ( bit Bit is unknown 2010 Microchip Technology Inc. ...
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... When ‘a’ is ‘0’, the address is interpreted as being a register in the Access Bank. Addressing that uses the Access RAM is sometimes also known as Direct Forced Addressing mode. 2010 Microchip Technology Inc. PIC18F2331/2431/4331/4431 A few instructions, such as MOVFF, include the entire 12-bit address (either source or destination) in their op codes. In these cases, the BSR is ignored entirely. The destination of the operation’ ...
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... FSRnH register. On the other hand, results of these operations do not change the value of any flags in the STATUS register (e.g OV, etc.). ADDWF, INDF1, 1 FSR1H:FSR1L 000h Bank 0 100h Bank 1 200h Bank 2 300h 0 Bank 3 through Bank 13 E00h Bank 14 F00h Bank 15 FFFh Data Memory 2010 Microchip Technology Inc. ...
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... INDF1. Attempts to read the value of the INDF1 using INDF0 as an operand will return 00h. Attempts to write to INDF1 using INDF0 as the operand will result in a NOP. 2010 Microchip Technology Inc. PIC18F2331/2431/4331/4431 On the other hand, using the virtual registers to write to an FSR pair may not occur as planned. In these cases, the value will be written to the FSR pair but without any incrementing or decrementing ...
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... PIC18F2331/2431/4331/4431 NOTES: DS39616D-page 78 2010 Microchip Technology Inc. ...
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... Characteristics”) for exact limits. “Electrical 7.1 EEADR The Address register can address 256 bytes of data EEPROM. 2010 Microchip Technology Inc. PIC18F2331/2431/4331/4431 7.2 EECON1 and EECON2 Registers Access to the data EEPROM is controlled by two registers: EECON1 and EECON2. These are the same range ...
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... When a WRERR occurs, the EEPGD and CFGS bits are not cleared. This allows tracing of the error Note 1: condition. DS39616D-page 80 R/W-0 R/W-x R/W-0 (1) FREE WRERR WREN U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) R/S-0 R/S bit Bit is unknown 2010 Microchip Technology Inc. ...
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... EECON1, WR GOTO $-2 BSF INTCON, GIE 2010 Microchip Technology Inc. PIC18F2331/2431/4331/4431 After a write sequence has been initiated, EECON1, EEADR and EEDATA cannot be modified. The WR bit will be inhibited from being set unless the WREN bit is set. The WREN bit must be set on a previous instruc- tion ...
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... Set for memory ; Set for Data EEPROM ; Disable interrupts ; Enable writes ; Loop to refresh array ; Read current address ; ; Write 55h ; ; Write 0AAh ; Set WR bit to begin write ; Wait for write to complete ; Increment address ; Not zero again ; Disable writes ; Enable interrupts 2010 Microchip Technology Inc. ...
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... EEPGD CFGS IPR2 OSCFIP — PIR2 OSCFIF — PIE2 OSCFIE — Legend: — = unimplemented, read as ‘0’. Shaded cells are not used during Flash/EEPROM access. 2010 Microchip Technology Inc. PIC18F2331/2431/4331/4431 Bit 5 Bit 4 Bit 3 Bit 2 INT0IE RBIE TMR0IF — FREE WRERR WREN — ...
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... PIC18F2331/2431/4331/4431 NOTES: DS39616D-page 84 2010 Microchip Technology Inc. ...
Page 85
... TBLPTRL Program Memory (TBLPTR) Note 1: The Table Pointer points to a byte in program memory. 2010 Microchip Technology Inc. PIC18F2331/2431/4331/4431 The program memory space is 16 bits wide, while the data RAM space is 8 bits wide. Table reads and table writes move data between these two memory spaces DD through an 8-bit register (TABLAT) ...
Page 86
... The WR control bit initiates write operations. The bit cannot be cleared, only set, in software. The bit is cleared in hardware at the completion of the write operation. The EEIF interrupt flag bit (PIR2<4>) is Note: set when the write is complete. It must be cleared in software. CPU”.) Table Latch (8-bit) TABLAT 2010 Microchip Technology Inc. ...
Page 87
... RD bit cannot be set when EEPGD = 1 or CFGS = 1 Does not initiate an EEPROM read When a WRERR occurs, the EEPGD and CFGS bits are not cleared. This allows tracing of the error Note 1: condition. 2010 Microchip Technology Inc. PIC18F2331/2431/4331/4431 R/W-0 R/W-x R/W-0 ...
Page 88
... Operation on Table Pointer TBLPTR is not modified TBLPTR is incremented after the read/write TBLPTR is decremented after the read/write TBLPTR is incremented before the read/write TBLPTRH 8 7 TBLPTR<21:6> TABLE READ – TBLPTR<21:0> Section 8.5 Memory”. TBLPTRL 0 TABLE WRITE TBLPTR<5:0> 2010 Microchip Technology Inc. ...
Page 89
... WORD_EVEN TBLRD*+ MOVF TABLAT,W MOVWF WORD_ODD 2010 Microchip Technology Inc. PIC18F2331/2431/4331/4431 The internal program memory is typically organized by words. The Least Significant bit of the address selects between the high and low bytes of the word. shows the interface between the internal program memory and the TABLAT ...
Page 90
... TBLPTR with the base ; address of the memory block ; point to Flash program memory ; access Flash program memory ; enable write to memory ; enable Row Erase operation ; disable interrupts ; write 55H ; write 0AAH ; start erase (CPU stall) ; re-enable interrupts 2010 Microchip Technology Inc. ...
Page 91
... TABLE WRITES TO FLASH PROGRAM MEMORY 8 TBLPTR = xxxxx0 TBLPTR = xxxxx1 Holding Register 2010 Microchip Technology Inc. PIC18F2331/2431/4331/4431 The long write is necessary for programming the internal Flash. Instruction execution is halted while in a long write cycle. The long write will be terminated by the internal programming timer. ...
Page 92
... Execute a NOP. 14. Re-enable interrupts. 15. Repeat Steps 6-14 seven times to write 64 bytes. 16. Verify the memory (table read). This procedure will require about update one row of 64 bytes of memory. An example of the required code is given in Example 8-3. 2010 Microchip Technology Inc. ...
Page 93
... WRITE_WORD_TO_HREGS MOVF POSTINC0,F MOVWF TABLAT TBLWT+* DECFSZ COUNTER GOTO WRITE_WORD_TO_HREGS 2010 Microchip Technology Inc. PIC18F2331/2431/4331/4431 ; number of bytes in erase block ; point to buffer ; Load TBLPTR with the base ; address of the memory block ; 6 LSB = 0 ; read into TABLAT, and inc ; get data ; store data and increment FSR0 ...
Page 94
... RBIE TMR0IF — FREE WRERR WREN — EEIP — LVDIP — EEIF — LVDIF — EEIE — LVDIE for details on code protection of Flash Reset Bit 1 Bit 0 Values on Page INT0IF RBIF — CCP2IP 57 — CCP2IF 57 — CCP2IE 57 2010 Microchip Technology Inc. ...
Page 95
... Signed Hardware Multiply Without Hardware Multiply Unsigned Hardware Multiply Without Hardware Multiply Signed Hardware Multiply 2010 Microchip Technology Inc. PIC18F2331/2431/4331/4431 9.2 Operation Example 9-1 shows the sequence unsigned multiply. Only one instruction is required when one argument of the multiply is already loaded in the WREG register ...
Page 96
... MOVF ARG2H, W SUBWFB RES3 ; CONT_CODE : SIGNED MULTIPLICATION ALGORITHM SIGNED MULTIPLY ROUTINE ; ARG1L * ARG2L -> ; PRODH:PRODL ; ARG1H * ARG2H -> ; PRODH:PRODL ; ARG1L * ARG2H -> ; PRODH:PRODL ; ; Add cross ; products ; ; ; ; ; ARG1H * ARG2L -> ; PRODH:PRODL ; ; Add cross ; products ; ; ; ; ARG2H:ARG2L neg? ; no, check ARG1 ; ; ; ; ARG1H:ARG1L neg? ; no, done ; ; ; 2010 Microchip Technology Inc. ...
Page 97
... Individual interrupts can be disabled through their corresponding enable bits. 2010 Microchip Technology Inc. PIC18F2331/2431/4331/4431 When the IPEN bit is cleared (default state), the interrupt priority feature is disabled and interrupts are devices ...
Page 98
... INT2IF INT2IE INT2IP IPEN IPEN PEIE/GIEL IPEN TMR0IF TMR0IE TMR0IP RBIF RBIE RBIP INT0IF INT0IE INT1IF INT1IE INT1IP INT2IF INT2IE INT2IP 2010 Microchip Technology Inc. Wake- Power-Managed Mode Interrupt to CPU Vector to Location 0008h GIE/GIEH Interrupt to CPU Vector to Location 0018h PEIE/GIEL ...
Page 99
... RBIF: RB Port Change Interrupt Flag bit least one of the RB<7:4> pins changed state (must be cleared in software None of the RB<7:4> pins have changed state 2010 Microchip Technology Inc. PIC18F2331/2431/4331/4431 Interrupt flag bits are set when an interrupt Note: condition occurs, regardless of the state of its corresponding enable bit or the global enable bit ...
Page 100
... User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. This feature allows for software polling. DS39616D-page 100 R/W-1 U-0 R/W-1 INTEDG2 — TMR0IP U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared U-0 R/W-1 — RBIP bit Bit is unknown 2010 Microchip Technology Inc. ...
Page 101
... Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding Note: enable bit or the global enable bit. User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. This feature allows for software polling. 2010 Microchip Technology Inc. PIC18F2331/2431/4331/4431 R/W-0 R/W-0 ...
Page 102
... R-0 R/W-0 R/W-0 TXIF SSPIF CCP1IF U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Enable bit, GIE R/W-0 R/W-0 TMR2IF TMR1IF bit Bit is unknown 2010 Microchip Technology Inc. ...
Page 103
... A TMR1 register capture occurred (must be cleared in software TMR1 register capture occurred Compare mode TMR1 register compare match occurred (must be cleared in software TMR1 register compare match occurred PWM mode: Not used in this mode. 2010 Microchip Technology Inc. PIC18F2331/2431/4331/4431 R/W-0 U-0 R/W-0 EEIF — ...
Page 104
... Timer5 time base matched the PR5 value (must be cleared in software Timer5 time base did not match the PR5 value DS39616D-page 104 R/W-0 R/W-0 R/W-0 PTIF IC3DRIF IC2QEIF U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R/W-0 R/W-0 IC1IF TMR5IF bit Bit is unknown 2010 Microchip Technology Inc. ...
Page 105
... TMR2IE: TMR2 to PR2 Match Interrupt Enable bit 1 = Enables the TMR2 to PR2 match interrupt 0 = Disables the TMR2 to PR2 match interrupt bit 0 TMR1IE: TMR1 Overflow Interrupt Enable bit 1 = Enables the TMR1 overflow interrupt 0 = Disables the TMR1 overflow interrupt 2010 Microchip Technology Inc. PIC18F2331/2431/4331/4431 R/W-0 R/W-0 R/W-0 TXIE SSPIE CCP1IE U = Unimplemented bit, read as ‘ ...
Page 106
... Unimplemented: Read as ‘0’ bit 0 CCP2IE: CCP2 Interrupt Enable bit 1 = Enabled 0 = Disabled DS39616D-page 106 R/W-0 U-0 R/W-0 EEIE — LVDIE U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared U-0 R/W-0 — CCP2IE bit Bit is unknown 2010 Microchip Technology Inc. ...
Page 107
... IC1IE: IC1 Interrupt Enable bit 1 = IC1 interrupt enabled 0 = IC1 interrupt disabled bit 0 TMR5IE: Timer5 Interrupt Enable bit 1 = Timer5 interrupt enabled 0 = Timer5 interrupt disabled 2010 Microchip Technology Inc. PIC18F2331/2431/4331/4431 R/W-0 R/W-0 R/W-0 PTIE IC3DRIE IC2QEIE U = Unimplemented bit, read as ‘0’ ...
Page 108
... Low priority bit 0 TMR1IP: TMR1 Overflow Interrupt Priority bit 1 = High priority 0 = Low priority DS39616D-page 108 R/W-1 R/W-1 R/W-1 TXIP SSPIP CCPIP U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R/W-1 R/W-1 TMR2IP TMR1IP bit Bit is unknown 2010 Microchip Technology Inc. ...
Page 109
... LVDIP: Low-Voltage Detect Interrupt Priority bit 1 = High priority 0 = Low priority bit 1 Unimplemented: Read as ‘0’ bit 0 CCP2IP: CCP2 Interrupt Priority bit 1 = High priority 0 = Low priority 2010 Microchip Technology Inc. PIC18F2331/2431/4331/4431 R/W-1 U-0 R/W-1 EEIP — LVDIP U = Unimplemented bit, read as ‘0’ ...
Page 110
... Low priority bit 0 TMR5IP: Timer5 Interrupt Priority bit 1 = High priority 0 = Low priority DS39616D-page 110 R/W-1 R/W-1 R/W-1 PTIP IC3DRIP IC2QEIP U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R/W-1 R/W-1 IC1IP TMR5IP bit Bit is unknown 2010 Microchip Technology Inc. ...
Page 111
... PD: Power-Down Detection Flag bit For details of bit operation, see bit 1 POR: Power-on Reset Status bit For details of bit operation, see bit 0 BOR: Brown-out Reset Status bit For details of bit operation, see 2010 Microchip Technology Inc. PIC18F2331/2431/4331/4431 R/W-1 R-1 R Unimplemented bit, read as ‘0’ ...
Page 112
... WREG, STATUS and BSR registers during an Interrupt Service Routine. ; W_TEMP is in virtual bank ; STATUS_TEMP located anywhere ; BSR_TMEP located anywhere ; Restore BSR ; Restore WREG ; Restore STATUS Section 12.0 “Timer0 Module” Section 6.1.3 2010 Microchip Technology Inc. ...
Page 113
... PORT I/O pins have diode protection to V Note 1: 2010 Microchip Technology Inc. PIC18F2331/2431/4331/4431 11.1 PORTA, TRISA and LATA Registers PORTA is an 8-bit wide, bidirectional port. The corre- sponding data direction register is TRISA. Setting a TRISA bit (= 1) will make the corresponding PORTA pin an input (i ...
Page 114
... PORTA<6> data input. Enabled in RCIO, INTIO2 and ECIO modes only. I ANA Main oscillator input connection. I ANA Main clock input connection. O DIG LATA<7> data output. Disabled in external oscillator modes. I TTL PORTA<7> data input. Disabled in external oscillator modes. Description /4) in RC, INTIO1 and EC Oscillator OSC 2010 Microchip Technology Inc. ...
Page 115
... RA<7:6> and their associated latch and data direction bits are enabled as I/O pins based on oscillator Note 1: configuration; otherwise, they are read as ‘0’. ANS5 through ANS8 are available only on the PIC18F4331/4431 devices. 2: 2010 Microchip Technology Inc. PIC18F2331/2431/4331/4431 Bit 5 Bit 4 Bit 3 ...
Page 116
... RB<3:0> and RB4 pins are multiplexed with the 14-bit PWM module for PWM<3:0> and PWM5 output. The RB5 pin can be configured by the Configuration bit, PWM4MX, as the alternate pin for PWM4 output. 2010 Microchip Technology Inc. will end the ...
Page 117
... Don’t care (TRIS bit does not affect port direction or is overridden for this option). All other pin functions are disabled when ICSP or ICD is enabled. Note 1: Single-Supply Programming must be enabled. 2: RD5 is the alternate pin for PWM4. 3: 2010 Microchip Technology Inc. PIC18F2331/2431/4331/4431 I/O I/O Type O DIG LATB< ...
Page 118
... DS39616D-page 118 Bit 5 Bit 4 Bit 3 Bit 2 RB5 RB4 RB3 RB2 TMR0IE INT0IE RBIE TMR0IF INTEDG1 INTEDG2 — TMR0IP — INT2IE INT1IE — Reset Values Bit 1 Bit 0 on Page: RB1 RB0 INT0IF RBIF 54 — RBIP 54 INT2IF INT1IF 54 2010 Microchip Technology Inc. ...
Page 119
... The contents of the TRISC register are affected by peripheral overrides. Reading TRISC always returns the current contents, even though a peripheral device may be overriding one or more of the pins. 2010 Microchip Technology Inc. PIC18F2331/2431/4331/4431 External interrupts, IN0, INT1 and INT2, are placed on RC3, RC4 and RC5 pins, respectively. ...
Page 120
... Asynchronous serial transmit data output (EUSART module); takes priority over port data. User must configure as an output. O DIG Synchronous serial clock output (EUSART module); takes priority over port data Synchronous serial clock input (EUSART module SPI slave select input. Description 2010 Microchip Technology Inc. ...
Page 121
... PORTC Data Direction Register INTCON GIE/GIEH PEIE/GIEL INTCON2 RBPU INTEDG0 INTEDG1 INTEDG2 INTCON3 INT2IP INT1IP Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by PORTC. 2010 Microchip Technology Inc. PIC18F2331/2431/4331/4431 I/O I/O Type O DIG LATC<7> data output PORTC<7> data input. ...
Page 122
... EXAMPLE 11-4: INITIALIZING PORTD CLRF PORTD ; Initialize PORTD by ; clearing output ; data latches CLRF LATD ; Alternate method ; to clear output ; data latches MOVLW 0xCF ; Value used to ; initialize data ; direction MOVWF TRISD ; Set RD<3:0> as inputs ; RD<5:4> as outputs ; RD<7:6> as inputs 2010 Microchip Technology Inc. ...
Page 123
... TABLE 11-8: SUMMARY OF REGISTERS ASSOCIATED WITH PORTD Name Bit 7 Bit 6 Bit 5 PORTD RD7 RD6 LATD LATD Data Output Register TRISD PORTD Data Direction Register 2010 Microchip Technology Inc. PIC18F2331/2431/4331/4431 I/O I/O Type O DIG LATD<0> data output PORTD<0> data input Timer0 alternate clock input. ...
Page 124
... PORTE IN 28-PIN DEVICES For PIC18F2331/2431 devices, PORTE is not available only available for PIC18F4331/4431 devices. U-0 U-0 R/W-1 — — TRISE2 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared 2010 Microchip Technology Inc. R/W-1 R/W-1 TRISE1 TRISE0 bit Bit is unknown ...
Page 125
... Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by PORTE. Implemented only when Master Clear functionality is disabled (CONFIG3H<7> available for Note 1: PIC18F4331/4431 devices only. ANS5 through ANS8 are available only on PIC18F4331/4431 devices. 2: 2010 Microchip Technology Inc. PIC18F2331/2431/4331/4431 I/O I/O Type O DIG LATE< ...
Page 126
... PIC18F2331/2431/4331/4431 NOTES: DS39616D-page 126 2010 Microchip Technology Inc. ...
Page 127
... Prescale value 010 = 1:8 Prescale value 001 = 1:4 Prescale value 000 = 1:2 Prescale value 2010 Microchip Technology Inc. PIC18F2331/2431/4331/4431 Figure 12-1 shows a simplified block diagram of the Timer0 module in 8-bit mode and simplified block diagram of the Timer0 module in 16-bit mode. ...
Page 128
... Internal Clocks Programmable 0 Prescaler (2 T Delay Sync with Internal TMR0L Clocks Delay Set TMR0IF TMR0L on Overflow 8 8 Internal Data Bus Set TMR0 TMR0IF High Byte on Overflow 8 Read TMR0L Write TMR0L 8 8 TMR0H 8 8 Internal Data Bus 2010 Microchip Technology Inc. ...
Page 129
... TRISA7 TRISA6 Legend: Shaded cells are not used by Timer0. RA6 and RA7 are enabled as I/O pins depending on the oscillator mode selected in Configuration Word 1H. Note 1: 2010 Microchip Technology Inc. PIC18F2331/2431/4331/4431 12.2.1 SWITCHING PRESCALER ASSIGNMENT The prescaler assignment is fully under software con- trol (i.e., it can be changed “ ...
Page 130
... PIC18F2331/2431/4331/4431 NOTES: DS39616D-page 130 2010 Microchip Technology Inc. ...
Page 131
... Internal clock (F OSC bit 0 TMR1ON: Timer1 On bit 1 = Enables Timer1 0 = Stops Timer1 2010 Microchip Technology Inc. PIC18F2331/2431/4331/4431 Register 13-1 details the Timer1 Control register. This register controls the operating mode of the Timer1 module and contains the Timer1 Oscillator Enable bit (T1OSCEN). Timer1 can be enabled or disabled by setting or clearing control bit, TMR1ON (T1CON< ...
Page 132
... Special Event Trigger) 8 Trigger”). 1 Synchronize 0 Detect Sleep Input Timer1 On/Off Set TMR1 TMR1IF High Byte on Overflow 1 Synchronize 0 Detect Sleep Input Timer1 On/Off Set TMR1 TMR1IF High Byte on Overflow 8 Read TMR1L Write TMR1L 8 TMR1H 8 8 Internal Data Bus 2010 Microchip Technology Inc. ...
Page 133
... Capacitor values are for design guidance only. 2010 Microchip Technology Inc. PIC18F2331/2431/4331/4431 13.3 Timer1 Oscillator Layout Considerations The Timer1 oscillator for PIC18F2331/2431/4331/4431 devices incorporates an additional low-power feature. When this option is selected, it allows the oscillator to automatically reduce its power consumption when the microcontroller is in Sleep mode ...
Page 134
... For this method to be accurate, Timer1 must operate in Asynchronous mode and the Timer1 overflow interrupt must be enabled (PIE1<0> shown in the routine, RTCinit. The Timer1 oscillator must also be enabled and running at all times. Oscillator”) 2010 Microchip Technology Inc. ...
Page 135
... T1CON RD16 T1RUN T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the Timer1 module. 2010 Microchip Technology Inc. PIC18F2331/2431/4331/4431 ; Preload TMR1 register pair ; for 1 second overflow ; Configure for external clock, ; Asynchronous operation, external oscillator ...
Page 136
... Watchdog Timer Reset or Brown-out Reset) TMR2 is not cleared when T2CON is written. R/W-0 R/W-0 R/W-0 TOUTPS1 TOUTPS0 TMR2ON U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared /4) has a prescale option OSC R/W-0 R/W-0 T2CKPS1 T2CKPS0 bit Bit is unknown 2010 Microchip Technology Inc. ...
Page 137
... TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 PR2 Timer2 Period Register Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the Timer2 module. 2010 Microchip Technology Inc. PIC18F2331/2431/4331/4431 14.3 Output of TMR2 The unscaled output of TMR2 is available primarily to the CCP modules, where it is used as a time base for operations in PWM mode ...
Page 138
... PIC18F2331/2431/4331/4431 NOTES: DS39616D-page 138 2010 Microchip Technology Inc. ...
Page 139
... These bits are not implemented on PIC18F2331/2431 devices and read as ‘0’. Note 1: For Timer5 to operate during Sleep mode, T5SYNC must be set. 2: 2010 Microchip Technology Inc. PIC18F2331/2431/4331/4431 Timer5 is a general purpose timer/counter that incor- porates additional features for use with the Motion Feedback Module (see Module” ...
Page 140
... Timer5 prescaler divides the input not at all (1:1). The TMR5 register pair increments on Q1. Clearing TMR5CS (= 0) selects the internal device clock as the timer sampling clock. Module (Input 1 Internal Data Bus 0 Timer5 On/Off Write TMR5L Read TMR5L 8 8 2010 Microchip Technology Inc. ...
Page 141
... Timer5 is disabled and a Special Event Trigger Reset is present on the Timer5 Reset input. (See Section 15.7 “Timer5 Special Event Trigger for additional information.) Reset Input” 2010 Microchip Technology Inc. PIC18F2331/2431/4331/4431 15.2 16-Bit Read/Write and Write Modes As noted, the actual high byte of the Timer5 register pair is mapped to TMR5H, which serves as a buffer ...
Page 142
... INTERRUPT DETECT IN SLEEP MODE When configured as described above, Timer5 will continue to increment on each rising edge on T5CKI while in Sleep mode. When a TMR5/PR5 match occurs, an interrupt is generated which can wake the part. Section 17.1 “Input Capture”. 2010 Microchip Technology Inc. ...
Page 143
... Timer5 Period Register Low Byte T5CON T5SEN RESEN CAP1CON — CAP1REN DFLTCON — FLT4EN Legend: — = unimplemented. Shaded cells are not used by the Timer5 module. 2010 Microchip Technology Inc. PIC18F2331/2431/4331/4431 Bit 5 Bit 4 Bit 3 Bit 2 INT0IE RBIE TMR0IF — PTIP IC3DRIP IC2QEIP — ...
Page 144
... PIC18F2331/2431/4331/4431 NOTES: DS39616D-page 144 2010 Microchip Technology Inc. ...
Page 145
... Compare mode; initialize CCPx pin high; on compare match, force CCPx pin low (CCPxIF bit is set) 1010 = Compare mode; generate software interrupt on compare match (CCPxIF bit is set, CCPx pin is unaffected) 1011 = Compare mode; Special Event Trigger (CCPxIF bit is set) 11xx = PWM mode 2010 Microchip Technology Inc. PIC18F2331/2431/4331/4431 TABLE 16-1: CCP Mode Capture ...
Page 146
... Enable and TMR1H CCP2CON<3:0> Example 16-1 shows the recom- CHANGING BETWEEN CAPTURE PRESCALERS ; Turn CCP module off ; Load WREG with the ; new prescaler mode ; value and CCP ON ; Load CCP1CON with ; this value CCPR1L TMR1L CCPR2L TMR1L 2010 Microchip Technology Inc. ...
Page 147
... RC2/CCP1 Pin TRISC<2> Output Enable Q RC1/CCP2 Pin TRISC<1> Output Enable 2010 Microchip Technology Inc. PIC18F2331/2431/4331/4431 16.4.2 TIMER1 MODE SELECTION Timer1 must be running in Timer mode or Synchro- nized Counter mode if the CCP module is using the compare feature. In Asynchronous Counter mode, the compare operation may not work. ...
Page 148
... CCP2M3 CCP2M2 CCP2M1 CCP2M0 — EEIF — LVDIF — EEIE — LVDIE — EEIP — LVDIP Reset Values Bit 1 Bit 0 on Page: INT0IF RBIF 54 TMR2IF TMR1IF 57 TMR2IE TMR1IE 57 TMR2IP TMR1IP — CCP2IF 57 — CCP2IE 57 — CCP2IP 57 2010 Microchip Technology Inc. ...
Page 149
... FIGURE 16-4: PWM OUTPUT Period Duty Cycle TMR2 = PR2 TMR2 = Duty Cycle TMR2 = PR2 2010 Microchip Technology Inc. PIC18F2331/2431/4331/4431 16.5.1 PWM PERIOD The PWM period is specified by writing to the PR2 register. The PWM period can be calculated using the following equation: EQUATION 16-1: PWM Period = [(PR2 • ...
Page 150
... DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0 DC2B1 DC2B0 CCP2M3 CCP2M2 CCP2M1 CCP2M0 156.25 kHz 312.50 kHz 416.67 kHz 3Fh 1Fh 17h 8 7 6.58 Reset Values Bit 1 Bit 0 on Page: INT0IF RBIF 54 TMR2IF TMR1IF 57 TMR2IE TMR1IE 57 TMR2IP TMR1IP 2010 Microchip Technology Inc. ...
Page 151
... Counter Overflow Flag for Low Rotation Speed • Utilizes Input Capture 1 Logic (IC1) • High and Low Velocity Support 2010 Microchip Technology Inc. PIC18F2331/2431/4331/4431 Many of the features for the IC and QEI submodules are fully programmable, creating a flexible peripheral structure that can accommodate a wide range of in-system uses ...
Page 152
... Timer Reset Direction QEA Clock QEI Control CHGIF Logic INDX QEI Logic IC3DRIF IC3IF QEI Mode Decoder QEIF IC2QEIF IC2IF TMR5IF Special Event Trigger Output TMR5<15:0> 8 IC3IF 8 IC2IF 8 IC1IF Special Event Trigger Reset Position Counter QEIF 8 8 2010 Microchip Technology Inc. ...
Page 153
... Q Clocks Note 1: CAP1BUF register is reconfigured as VELR register when QEI mode is active. 2: QEI generated velocity pulses, vel_out, are downsampled to produce this velocity capture signal. 2010 Microchip Technology Inc. PIC18F2331/2431/4331/4431 Input Channel 1 (IC1) includes a Special Event Trigger that can be configured for use in Velocity Measurement mode ...
Page 154
... CAP3BUF is enabled as MAXCNT when QEI mode is active. DS39616D-page 154 and Mode Select Q Clocks (1) ICxIF (1) Capture Clock/ CAPxBUF_clk (1) Reset/ Interrupt Decode Logic Reset CAPxM<3:0> (1) Capture Clock (1,2,3) CAPxBUF TMR5 Enable TMR5 TMR5 Reset Timer Reset Control (2) CAPxREN 2010 Microchip Technology Inc. ...
Page 155
... Capture mode, every rising edge 0001 = Capture mode, every falling edge 0000 = Input Capture x (ICx) off Special Event Trigger is only available on CAP1. For CAP2 and CAP3, this configuration is unused. Note 1: 2010 Microchip Technology Inc. PIC18F2331/2431/4331/4431 Throughout this section, references to Note: registers, ...
Page 156
... BCF CAP1CON, CAP1REN . In the event that a write to TMR5 coincides with an input capture event, CY clock edge when the capture event takes place (see CY Figure 17-4). 17-4). 0002 0000 0001 0002 0003 0002 Note 5 2010 Microchip Technology Inc. ...
Page 157
... Pulse-Width Measurement mode active on each rising edge detected. In the falling to rising Pulse-Width Measurement mode active on each falling edge detected. 5: TMR5 Reset pulse is activated on the capture edge. The CAP1REN bit has no bearing in this mode. 2010 Microchip Technology Inc. PIC18F2331/2431/4331/4431 Timer5 is always reset on the edge when the measurement is first initiated ...
Page 158
... Any change on CAP1, CAP2 or CAP3 is detected and the associated time base count is captured For position and velocity measurement in this mode, the timer can be optionally reset (see “Timer5 Reset” Section 17.1.6 for Reset options). Figure 17-4. There 2010 Microchip Technology Inc. ...
Page 159
... With the Special Event Trigger Reset disabled, Timer5 cannot be reset by the Special Event Trigger Reset on the CAP1 input. In order for the Special Event Trigger Reset to work as the Reset trigger to Timer5, IC1 must be configured in the Special Event Trigger mode (CAP1M<3:0> = 1110 or 1111). 2010 Microchip Technology Inc. PIC18F2331/2431/4331/4431 17.1.6 ...
Page 160
... Captures Timer5 on state change. (1) TMR5 optional Simple Edge Capture mode (includes a selectable prescaler). (1) TMR5 optional Captures Timer5 on period boundaries. TMR5 always Captures Timer5 on pulse boundaries. (1) TMR5 optional Captures Timer5 on state change. Section 17.2.6 “Velocity Description 2010 Microchip Technology Inc. ...
Page 161
... CAP3/QEB Filter CAP2/QEA Filter CAP1/INDX 2010 Microchip Technology Inc. PIC18F2331/2431/4331/4431 The QEI control logic detects the leading edge on the QEA or QEB phase input pins and generates the count pulse, which is sent to the position counter logic. It also samples the index input signal (INDX) and generates the direction of the rotation signal (up/down) and the velocity event signals ...
Page 162
... QEI will take precedence and IC will remain disabled. R/W-0 R/W-0 R/W-0 (2,3) (2,3) QEIM2 QEIM1 QEIM0 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (4) (2,3) Register 17-2). R/W-0 R/W-0 (2,3) PDEC1 PDEC0 bit Bit is unknown 2010 Microchip Technology Inc. ...
Page 163
... QEA and QEB edge. Like QEI x2 mode, the position counter can be reset by an input on the pin (QEIM<2:0> = 101 the period match event (QEIM<2:0> = 010). 2010 Microchip Technology Inc. PIC18F2331/2431/4331/4431 17.2.3 QEI OPERATION The Position Counter register pair (POSCNTH: ...
Page 164
... Update mode 1024) with F to 2.5 MHz, which corresponds to F Figure 17-9 shows QEA and QEB quadrature input timing when sampled by the noise filter. 17-11 directly proportional to POS = 4D • RPM POS MIPS is equal CY of 625 kHz. QEI 2010 Microchip Technology Inc. ...
Page 165
... POSCNT = 0 (when decrementing), which occurs on the next QEA falling edge. 3: IC2QEIF is generated on the Q4 rising edge. 4: Position counter is loaded with ‘0’ (which is a rollover event in this case) on POSCNT = MAXCNT. 5: Position counter is loaded with MAXCNT value (1527h) on underflow. 6: IC2QEIF must be cleared in software. 2010 Microchip Technology Inc. PIC18F2331/2431/4331/4431 ( ...
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... The position counter is loaded with a MAXCNT value (e.g., 1527h) on the next QEA or QEB edge following the INDX falling edge input signal detect). 6: IC2QEIF must be cleared in software. DS39616D-page 166 Reverse Note Note 6 (3) (3) Q4 (5) (4) Q1 clock cycle. CY 2010 Microchip Technology Inc. ...
Page 167
... Velocity Event CAP3/QEB QEB QEA CAP2/QEA INDX CAP1/INDX 2010 Microchip Technology Inc. PIC18F2331/2431/4331/4431 17.2.6.1 Velocity Event Timing The event pulses are reduced by a fixed ratio by the velocity pulse divider. The divider is useful for high-speed measurements where the velocity events happen frequently. By producing a single output pulse for a given number of input event pulses, the counter can track larger pulse counts (i ...
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... CAP1REN bit (CAP1CON<6>). When CAP1REN is cleared, the TMR5 time base will not be reset on any velocity event capture pulse. The VELR register pair, however, will continue to be updated with the current TMR5 value. Q1 (5) 2010 Microchip Technology Inc. ...
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... The noise filter output enables are functional in both QEI and IC Operating modes. Note 1: The noise filter is intended for random high-frequency filtering and not continuous high-frequency filtering. Note: 2010 Microchip Technology Inc. PIC18F2331/2431/4331/4431 programmed by the FLTCK<2:0> Configuration bits used as the clock reference to the clock divider CY block ...
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... If the CAPx interrupt is enabled, the device will wake-up from Sleep. This effectively enables all input a velocity capture channels to be used as the external interrupts. 17.5.2 QEI IN SLEEP MODE All QEI functions are halted in Sleep mode. Update QEI CY (3) Noise Glitch 2010 Microchip Technology Inc. ...
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... QERR Legend: — = unimplemented. Shaded cells are not used by the Motion Feedback Module. Register name and function determined by which submodule is selected (IC/QEI, respectively). See Note 1: Section 17.1.10 “Other Operating Modes” 2010 Microchip Technology Inc. PIC18F2331/2431/4331/4431 Bit 5 Bit 4 Bit 3 Bit 2 ...
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... PIC18F2331/2431/4331/4431 NOTES: DS39616D-page 172 2010 Microchip Technology Inc. ...
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... Switched Reluctance Motors • Brushless DC (BLDC) Motors • Uninterruptible Power Supplies (UPS) • Multiple DC Brush Motors 2010 Microchip Technology Inc. PIC18F2331/2431/4331/4431 The PWM module has the following features: • eight PWM I/O pins with four duty cycle generators. Pins can be paired to get a complete half-bridge control ...
Page 174
... PWM Channel 1 Generator 1 Dead-Time Generator and Override Logic PWM Channel 0 Generator 0 Dead-Time Generator and Override Logic Special Event Special Event Trigger Postscaler (2) PWM7 (2) (2) PWM6 PWM5 Output PWM4 Driver Block PWM3 PWM2 PWM1 PWM0 FLTA (2) FLTB 2010 Microchip Technology Inc. ...
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... In Complementary modes, the even PWM pins must always be the complement of the corresponding odd PWM pin. For example, PWM0 will be the complement of PWM1, PWM2 will be the complement of PWM3 and so on. The dead-time 2010 Microchip Technology Inc. PIC18F2331/2431/4331/4431 V DD Dead-Band ...
Page 176
... The PWM time base is configured through the PTCON0 and PTCON1 registers. The time base is enabled or disabled by respectively setting or clearing the PTEN bit in the PTCON1 register. The PTMR register pair (PTMRL:PTMRH) Note: is not cleared when the PTEN bit is cleared in software. 2010 Microchip Technology Inc. Figure 18-4. ...
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... The PWM time base can be configured for four different modes of operation: • Free-Running mode • Single-Shot mode • Continuous Up/Down Count mode • Continuous Up/Down Count mode with interrupts for double updates 2010 Microchip Technology Inc. PIC18F2331/2431/4331/4431 PTMR Clock Timer Reset Up/Down Zero Match Timer ...
Page 178
... OSC /256 (1:64 prescale) OSC U-0 U-0 U-0 — — — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R/W-0 R/W-0 PTMOD1 PTMOD0 bit Bit is unknown U-0 U-0 — — bit Bit is unknown 2010 Microchip Technology Inc. ...
Page 179
... When PWMEN<2:0> = 101, PWM<5:0> outputs are enabled for PIC18F2331/2431 devices; PWM<7:0> 2: outputs are enabled for PIC18F4331/4431 devices. When PWMEN<2:0> = 111, PWM Outputs 1, 3 and 5 are enabled in PIC18F2331/2431 devices; PWM Outputs and 7 are enabled in PIC18F4331/4431 devices. Unimplemented in PIC18F2331/2431 devices; maintain these bits clear. 3: 2010 Microchip Technology Inc. PIC18F2331/2431/4331/4431 (1) R/W-1 R/W-0 R/W-0 (3) ...
Page 180
... Write to the PTMR register • Write to the PTCON (PTCON0 or PTCON1) register • Any device Reset The PTMR register is not cleared when Note: PTCONx is written. timer counts U-0 R/W-0 R/W-0 — UDIS OSYNC bit Bit is unknown /4) has prescaler OSC 2010 Microchip Technology Inc. ...
Page 181
... Qc Qc PTMR FFEh PTMR_INT_REQ PTIF bit Note 1: PWM Time Base Period register, PTPER, is loaded with the value, FFFh, for this example. 2010 Microchip Technology Inc. PIC18F2331/2431/4331/4431 18.3.5 PWM TIME BASE POSTSCALER The match output of PTMR can optionally MHz postscaled through a 4-bit postscaler (which gives a 1:1 to 1:16 scaling inclusive) to generate an interrupt ...
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... The postscaler selection bits may be used in this mode of the timer to reduce the frequency of the interrupt events. Figure 18-7 Up/Down Count mode FFFh 000h FFFh 000h 1 Up/Down Count mode shows the interrupts in Continuous 000h 000h 000h 000h 2010 Microchip Technology Inc. ...
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... PWM TIME BASE INTERRUPT, CONTINUOUS UP/DOWN COUNT MODE A: PRESCALER = 1 OSC PTMR 002h PTDIR bit PTMR_INT_REQ 1 1 PTIF bit B: PRESCALER = 1 002h PTMR PTDIR bit 1 1 PTMR_INT_REQ PTIF bit Note 1: Interrupt flag bit, PTIF, is sampled here (every Q1). 2010 Microchip Technology Inc. PIC18F2331/2431/4331/4431 001h 000h 001h 000h ...
Page 184
... PTEN is active; it will yield unexpected results. To change the PWM Timer mode of operation, first clear the PTEN bit, load the PTMOD bits with the required data and then set PTEN. shows the 3FEh 3FFh 001h 000h 3FEh 3FDh 001h 002h 2010 Microchip Technology Inc. ...
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... The PWM frequency is the inverse of period; or: EQUATION 18-3: PWM FREQUENCY 1 PWM Frequency = PWM Period 2010 Microchip Technology Inc. PIC18F2331/2431/4331/4431 The maximum resolution (in bits) for a given device oscillator and PWM frequency can be determined from the following formula: EQUATION 18-4: Resolution = The PWM resolutions and frequencies are shown for a ...
Page 186
... PWM PERIOD BUFFER UPDATES IN CONTINUOUS UP/DOWN COUNT MODE New PTPER Value = 007 Old PTPER Value = 004 1 0 DS39616D-page 186 Period Value Loaded from PTPER Register New Value Written to PTPER Register Period Value Loaded from PTPER Register New Value Written to PTPER Register 2010 Microchip Technology Inc. ...
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... duty cycle match occurs duty cycle match occurs duty cycle match occurs on Q4 2010 Microchip Technology Inc. PIC18F2331/2431/4331/4431 The value in each Duty Cycle register determines the amount of time that the PWM output is in the active state. The upper 12 bits of PDCx holds the actual duty cycle value from PTMRH/L< ...
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... FIGURE 18-12: PTPER PTMR PDCx Value (old) PDCx (new) 0 Duty Cycle shows Active at Beginning of Period Duty Cycle Value Loaded from Buffer Register New Value Written to Duty Cycle Buffer Figure 18-12). EDGE-ALIGNED PWM New Duty Cycle Latched Period 2010 Microchip Technology Inc. ...
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... Duty Cycle Start of First PWM Period 2010 Microchip Technology Inc. PIC18F2331/2431/4331/4431 New Values Written to Duty Cycle Buffer inactive for the entire PWM period. In addition, the output on the PWM pin will be active for the entire PWM period if the value in the Duty Cycle register is equal to or greater than the value in the PTPER register ...
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... COMPLEMENTARY PWM OUTPUTS +V The Complementary mode is selected for each PWM I/O pin pair by clearing the appropriate PMODx bit in the PWMCON0 register. The PWM I/O pins are set to Complementary mode by default upon all kinds of device Resets. 2010 Microchip Technology Inc. 3-Phase Load ...
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... FIGURE 18-18: DEAD-TIME INSERTION FOR COMPLEMENTARY PWM PDC1 Compare Output PWM1 PWM0 2010 Microchip Technology Inc. PIC18F2331/2431/4331/4431 18.7.1 DEAD-TIME INSERTION Each complementary output pair for the PWM module has a 6-bit down counter used to produce the dead-time insertion. As shown in dead-time unit has a rising and falling edge detector connected to the duty cycle comparison output ...
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... Q clock corresponding to the Q clocks on which the PWM duty cycle match occurs. R/W-0 R/W-0 DT1 DT0 bit Bit is unknown /4, OSC /16, F /64, F /256 OSC OSC OSC /4) and OSC /2 OSC /4, OSC 2010 Microchip Technology Inc. ...
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... OSC 4 /16 OSC 2010 Microchip Technology Inc. PIC18F2331/2431/4331/4431 18.7.4 DEAD-TIME DISTORTION Note 1: For small PWM duty cycles, the ratio of dead time to the active PWM time may become large. In this case, the inserted dead time will introduce distortion into waveforms produced by the PWM module ...
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... Dead time is inserted in the PWM channels even when they are in Override mode. eight bits, POVD<7:0>, that Figure 18-20. 2010 Microchip Technology Inc. ...
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... Odd override bit is activated, which causes the even PWM to deactivate. 3. Dead-time insertion. 4. Odd PWM activated after the dead time. 5. Odd override bit is deactivated, which causes the odd PWM to deactivate. 6. Dead-time insertion. 7. Even PWM is activated after the dead time. 2010 Microchip Technology Inc. PIC18F2331/2431/4331/4431 DS39616D-page 195 ...
Page 196
... POUT4 POUT3 POUT2 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared the commutation sequence. Table 18-4 show the OVDCOND and OVDCONS R/W-1 R/W-1 POVD1 POVD0 bit Bit is unknown R/W-0 R/W-0 POUT1 POUT0 bit Bit is unknown 2010 Microchip Technology Inc. ...
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... TABLE 18-5: PWM OUTPUT OVERRIDE EXAMPLE #2 State OVDCOND (POVD) OVDCONS (POUT) 1 11000011b 00000000b 2 11110000b 00000000b 3 00111100b 00000000b 4 00001111b 00000000b 2010 Microchip Technology Inc. PIC18F2331/2431/4331/4431 FIGURE 18-22 PWM7 PWM6 PWM5 PWM4 PWM3 PWM2 PWM1 PWM0 PWM OUTPUT OVERRIDE EXAMPLE # DS39616D-page 197 ...
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... Fault inputs or manual override (see Section 18.10 “PWM Output The default polarity Configuration bits have the PWM I/O pins in active-high output polarity TRIS Latch and V . PWM polarity selection logic not shown for clarity Override”). I/O Pin TTL or Schmitt Trigger 2010 Microchip Technology Inc. ...
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... The inactive state of the PWM pins are Note: dependent on the HPOL and LPOL Con- figuration bit settings, which define the active and inactive state for PWM outputs. 2010 Microchip Technology Inc. PIC18F2331/2431/4331/4431 18.12.1 FAULT PIN ENABLE BITS By setting the bits, FLTAEN and FLTBEN in the FLTCONFIG register, the corresponding Fault inputs are enabled ...
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... If BRFEN = 0, the Fault condition on breakpoint is disabled highly recommended to enable the Note: Fault condition on breakpoint if a debug- ging tool is used while developing the firmware and high-power circuitry. When the device is ready to program after debugging the firmware, the BRFEN bit can be disabled. 2010 Microchip Technology Inc. ...