PIC18F4431-E/ML Microchip Technology, PIC18F4431-E/ML Datasheet - Page 169

• Manufacturer Part Number: PIC18F4431-E/ML
• Description: IC MCU FLASH 8KX16 44QFN
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F4431-E/ML

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, Power Control PWM, QEI, POR, PWM, WDT
• Number Of I /o: 36
• Program Memory Size: 16KB (8K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 768 x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 9x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 44-QFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

17.3
The Motion Feedback Module includes three noise
rejection
RA3/AN3/V
The filter block also includes a fourth filter for the T5CKI
pin. They are intended to help reduce spurious noise
spikes which may cause the input signals to become
corrupted at the inputs. The filter ensures that the input
signals are not permitted to change until a stable value
has been registered for three consecutive sampling
clock cycles.
The filters are controlled using the Digital Filter Control
(DFLTCON) register (see
can be individually enabled or disabled by setting or
clearing the corresponding FLTxEN bit in the
DFLTCON register. The sampling frequency, which
must be the same for all three noise filters, can be
REGISTER 17-3:
 2010 Microchip Technology Inc.
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2-0
Note 1:
Note:
U-0
—
Noise Filters
REF
filters
The noise filter output enables are functional in both QEI and IC Operating modes.
The noise filter is intended for random high-frequency filtering and not continuous high-frequency filtering.
Unimplemented: Read as ‘0’
FLT4EN: Noise Filter Output Enable bit (T5CKI input)
1 = Enabled
0 = Disabled
FLT3EN: Noise Filter Output Enable bit (CAP3/QEB input)
1 = Enabled
0 = Disabled
FLT2EN: Noise Filter Output Enable bit (CAP2/QEA input)
1 = Enabled
0 = Disabled
FLT1EN: Noise Filter Output Enable bit (CAP1/INDX Input)
1 = Enabled
0 = Disabled
FLTCK<2:0>: Noise Filter Clock Divider Ratio bits
111 = Unused
110 = 1:128
101 = 1:64
100 = 1:32
011 = 1:16
010 = 1:4
001 = 1:2
000 = 1:1
+/CAP2/QEA and RA4/AN4/CAP3/QEB.
FLT4EN
R/W-0
on
DFLTCON: DIGITAL FILTER CONTROL REGISTER
RA2/AN2/V
Register
W = Writable bit
‘1’ = Bit is set
FLT3EN
R/W-0
17-3). The filters
REF
(1)
-/CAP1/INDX,
PIC18F2331/2431/4331/4431
FLT2EN
R/W-0
(1)
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
FLT1EN
R/W-0
programmed by the FLTCK<2:0> Configuration bits.
T
block.
The noise filters can either be added or removed from
the input capture, or QEI signal path, by setting or
clearing the appropriate FLTxEN bit, respectively. Each
capture channel provides for individual enable control
of the filter output. The FLT4EN bit enables or disables
the noise filter available on the T5CKI input in the
Timer5 module.
The filter network for all channels is disabled on
Power-on and Brown-out Resets, as the DFLTCON
register is cleared on Resets. The operation of the filter
is shown in the timing diagram in
CY
is used as the clock reference to the clock divider
(1)
(1)
(1)
(1)
FLTCK2
R/W-0
x = Bit is unknown
FLTCK1
R/W-0
Figure
DS39616D-page 169
17-14.
FLTCK0
R/W-0
bit 0