PIC18F4431-E/ML Microchip Technology, PIC18F4431-E/ML Datasheet - Page 386

• Manufacturer Part Number: PIC18F4431-E/ML
• Description: IC MCU FLASH 8KX16 44QFN
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F4431-E/ML

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, Power Control PWM, QEI, POR, PWM, WDT
• Number Of I /o: 36
• Program Memory Size: 16KB (8K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 768 x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 9x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 44-QFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

PIC18F2331/2431/4331/4431
Timer2 ............................................................................... 136
Timer5 ............................................................................... 139
Timing Diagrams
DS39616D-page 386
Associated Registers ................................................ 137
Interrupt..................................................................... 137
Operation .................................................................. 136
Postscaler. See Postscaler, Timer2.
Prescaler. See Prescaler, Timer2.
PR2 Register............................................................. 136
SSP Clock Shift................................................. 136, 137
TMR2 Register .......................................................... 136
TMR2 to PR2 Match Interrupt ........................... 136, 149
Associated Registers ................................................ 143
Interrupt..................................................................... 142
Noise Filter ................................................................ 142
Operation .................................................................. 140
Prescaler ................................................................... 141
Special Event Trigger
16-Bit Read/Write and Write Modes ......................... 141
16-Bit Read-Modify-Write.......................................... 141
Automatic Baud Rate Calculation ............................. 225
Auto-Wake-up Bit (WUE) During
Auto-Wake-up Bit (WUE) During Sleep .................... 231
Brown-out Reset (BOR) ............................................ 349
Capture/Compare/PWM (All CCP Modules) ............. 352
CAPx Interrupts and IC1 Special Event Trigger........ 159
CLKO and I/O ........................................................... 348
Clock, Instruction Cycle .............................................. 65
Dead-Time Insertion for Complementary PWM ........ 191
Duty Cycle Update Times in Continuous
Duty Cycle Update Times in Continuous
Edge Capture Mode .................................................. 156
Edge-Aligned PWM................................................... 188
EUSART Asynchronous Reception .......................... 230
EUSART Asynchronous Transmission ..................... 227
EUSART Asynchronous Transmission
EUSART Synchronous Receive (Master/Slave) ....... 360
EUSART Synchronous Reception
EUSART Synchronous Transmission ....................... 233
EUSART Synchronous Transmission
EUSART SynchronousTransmission
Example SPI Master Mode (CKE = 0) ...................... 353
Example SPI Master Mode (CKE = 1) ...................... 354
Example SPI Slave Mode (CKE = 0) ........................ 355
Example SPI Slave Mode (CKE = 1) ........................ 356
External Clock (All Modes Except PLL) .................... 346
Fail-Safe Clock Monitor............................................. 278
Input Capture on State Change, Hall Effect
I
I
I
I
2
2
2
2
C Bus Data ............................................................. 357
C Bus Start/Stop Bits.............................................. 357
C Reception (7-Bit Address)................................... 214
C Transmission (7-Bit Address) ............................. 215
Continuous Count and Single-Shot................... 141
Sleep Mode....................................................... 142
Output ............................................................... 142
Reset Input........................................................ 142
Normal Operation.............................................. 231
Up/Down Count Mode....................................... 188
Up/Down Count Mode with
Double Updates ................................................ 189
(Back to Back)................................................... 227
(Master Mode, SREN)....................................... 235
(Through TXEN)................................................ 234
(Master/Slave)................................................... 360
Sensor Mode.................................................... 158
Timing Diagrams and Specifications ................................ 346
Low-Voltage Detect .................................................. 260
Low-Voltage Detect Characteristics.......................... 342
Noise Filter................................................................ 170
Pulse-Width Measurement Mode ............................. 157
PWM Output ............................................................. 149
PWM Output Override (Example 1) .......................... 197
PWM Output Override (Example 2) .......................... 197
PWM Override Bits in Complementary Mode ........... 195
PWM Period Buffer Updates in
PWM Period Buffer Updates in
PWM Time Base Interrupt, Continuous
PWM Time Base Interrupt, Continuous
PWM Time Base Interrupt, Free-Running Mode ...... 181
PWM Time Base Interrupt, Single-Shot Mode.......... 182
QEI Inputs When Sampled by Filter ......................... 165
QEI Reset on Period Match ...................................... 165
QEI Reset with the Index Input ................................. 166
Reset, Watchdog Timer (WDT), Oscillator
Send Break Character Sequence ............................. 232
Slow Rise Time (MCLR Tied to V
SPI Mode (Master Mode).......................................... 210
SPI Mode (Slave Mode with CKE = 0)...................... 210
SPI Mode (Slave Mode with CKE = 1)...................... 211
Start of Center-Aligned PWM ................................... 189
Time-out Sequence on POR w/PLL Enabled
Time-out Sequence on Power-up
Time-out Sequence on Power-up
Time-out Sequence on Power-up
Timer0 and Timer1 External Clock ........................... 351
Transition for Entry to Idle Mode................................. 44
Transition for Entry to SEC_RUN Mode ..................... 41
Transition for Entry to Sleep Mode ............................. 43
Transition for Two-Speed Start-up
Transition for Wake From Idle to Run Mode............... 44
Transition for Wake From Sleep (HSPLL) .................. 43
Transition From RC_RUN Mode to
Transition From SEC_RUN Mode to
Transition to RC_RUN Mode ...................................... 42
Velocity Measurement .............................................. 168
Capture/Compare/PWM Requirements
CLKO and I/O Requirements.................................... 348
EUSART Synchronous Receive Requirements........ 360
EUSART Synchronous Transmission
Example SPI Mode Requirements
Example SPI Mode Requirements
Continuous Up/Down Count Mode ................... 186
Free-Running Mode.......................................... 186
Up/Down Count Mode ...................................... 183
Up/Down Count Mode with
Double Updates................................................ 184
Start-up Timer (OST), Power-up
Timer (PWRT) .................................................. 349
V
(MCLR Tied to V
(MCLR Not Tied to V
(MCLR Not Tied to V
(MCLR Tied to V
(INTOSC to HSPLL) ......................................... 276
PRI_RUN Mode.................................................. 42
PRI_RUN Mode (HSPLL) ................................... 41
(All CCP Modules) ............................................ 352
Requirements ................................................... 360
(Master Mode, CKE = 0)................................... 353
(Master Mode, CKE = 1)................................... 354
DD
Rise > T
PWRT
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DD
DD
) ............................................. 52
) ........................................... 53
, V
DD
DD
DD
): Case 1 ....................... 51
): Case 2 ....................... 52
Rise T
DD
,
PWRT
) ............... 51