PIC18F4431-E/ML Microchip Technology, PIC18F4431-E/ML Datasheet - Page 170

• Manufacturer Part Number: PIC18F4431-E/ML
• Description: IC MCU FLASH 8KX16 44QFN
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F4431-E/ML

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, Power Control PWM, QEI, POR, PWM, WDT
• Number Of I /o: 36
• Program Memory Size: 16KB (8K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 768 x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 9x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 44-QFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

PIC18F2331/2431/4331/4431
FIGURE 17-14:
17.4
The IC and QEI submodules can each generate three
distinct interrupt signals; however, they share the use
of the same three interrupt flags in register, PIR3. The
meaning of a particular interrupt flag at any given time
depends on which module is active at the time the
interrupt is set. The meaning of the flags in context are
summarized in
When the IC submodule is active, the three flags (IC1IF,
IC2QEIF and IC3DRIF) function as interrupt-on-capture
event flags for their respective input capture channels.
The channel must be configured for one of the events
that will generate an interrupt (see
Interrupts”
When the QEI is enabled, the IC1IF interrupt flag
indicates
measurement event, usually an update of the VELR
register. The IC2QEIF interrupt indicates that a position
measurement event has occurred. IC3DRIF indicates
that a direction change has been detected.
TABLE 17-7:
DS39616D-page 170
Interrupt
IC1IF
IC2QEIF IC2 Capture Event
IC3DRIF IC3 Capture Event
CAP1/INDX Pin
(input to filter)
CAP1/INDX Input
(output from filter)
Flag
Note 1: Only the CAP1/INDX pin input is shown for simplicity. Similar event timing occurs on the CAP2/QEA and
IC and QEI Shared Interrupts
2: Noise filtering occurs in the shaded portions of the CAP1 input.
3: Filter’s group delay: T
IC1 Capture Event Velocity Register Update
an
for more information).
CAP3/QEB pins.
T
IC Mode
Table
CY
(1)
interrupt
(2)
MEANING OF IC AND QEI
INTERRUPT FLAGS
T
GD
17-7.
= 3 T
NOISE FILTER TIMING DIAGRAM (CLOCK DIVIDER = 1:1)
CY
Meaning
caused
Position Measurement
GD
Direction Change
Section 17.1.7 “IC
= 3 T
QEI Mode
by
Update
Noise Glitch
CY
.
a
velocity
(3)
17.5
17.5.1
Since the input capture can operate only when its time
base is configured in a Synchronous mode, the input
capture will not capture any events. This is because the
device’s internal clock has been stopped and any inter-
nal timers in Synchronous modes will not increment.
The prescaler will continue to count the events (not
synchronized).
When the specified capture event occurs, the CAPx
interrupt will be set. The Capture Buffer register will be
updated upon wake-up from sleep to the current TMR5
value. If the CAPx interrupt is enabled, the device will
wake-up from Sleep. This effectively enables all input
capture channels to be used as the external interrupts.
17.5.2
All QEI functions are halted in Sleep mode.
Operation in Sleep Mode
3x INPUT CAPTURE IN SLEEP
MODE
QEI IN SLEEP MODE
Noise Glitch
T
QEI
= 16 T
 2010 Microchip Technology Inc.
(3)
CY