Manufacturer Part NumberTS80C51RA2-VCA
DescriptionIC MCU 8BIT 256BYTE 40MHZ 40-DIP
TS80C51RA2-VCA datasheets

Specifications of TS80C51RA2-VCA

Core Processor8051Core Size8-Bit
PeripheralsPOR, PWM, WDTNumber Of I /o32
Program Memory TypeROMlessRam Size256 x 8
Voltage - Supply (vcc/vdd)4.5 V ~ 5.5 VOscillator TypeInternal
Operating Temperature0°C ~ 70°CPackage / Case40-DIP (0.600", 15.24mm)
Lead Free Status / RoHS StatusContains lead / RoHS non-compliantEeprom Size-
Program Memory Size-Data Converters-
Page 1
Page 2
Page 3
Page 4
Page 5
Page 6
Page 7
Page 8
Page 9
Page 10
Page 1/86

Download datasheet (988Kb)Embed
1. Features
80C52 Compatible
– 8051 pin and instruction compatible
– Four 8-bit I/O ports
– Three 16-bit timer/counters
– 256 bytes scratchpad RAM
High-Speed Architecture
– 40 MHz @ 5V, 30MHz @ 3V
– X2 Speed Improvement capability (6 clocks/machine cycle)
– 30 MHz @ 5V, 20 MHz @ 3V (Equivalent to
– 60 MHz @ 5V, 40 MHz @ 3V)
Dual Data Pointer
On-chip ROM/EPROM (16K-bytes, 32K-bytes, 64K-bytes)
On-chip eXpanded RAM (XRAM) (256 or 768 bytes)
Programmable Clock Out and Up/Down Timer/Counter 2
Programmable Counter Array with
– High Speed Output,
– Compare / Capture,
– Pulse Width Modulator,
– Watchdog Timer Capabilities
Hardware Watchdog Timer (One-time enabled with Reset-Out)
2 extra 8-bit I/O ports available on RD2 with high pin count packages
Asynchronous port reset
Interrupt Structure with
– 7 Interrupt sources,
– 4 level priority interrupt system
Full duplex Enhanced UART
– Framing error detection
– Automatic address recognition
Low EMI (inhibit ALE)
Power Control modes
– Idle mode
– Power-down mode
– Power-off Flag
Once mode (On-chip Emulation)
Power supply: 4.5-5V, 2.7-5.5V
Temperature ranges: Commercial (0 to 70
Packages: PDIL40, PLCC44, VQFP44 1.4, PLCC68, VQFP64 1.4
2. Description
Atmel TS8xC51Rx2 is a high performance CMOS ROM, OTP, EPROM and ROMless
versions of the 80C51 CMOS single chip 8-bit microcontroller.
The TS8xC51Rx2 retains all features of the 80C51 with extended ROM/EPROM
capacity (16/32/64 Kbytes), 256 bytes of internal RAM, a 7-source , 4-level interrupt
system, an on-chip oscilator and three timer/counters.
In addition, the TS80C51Rx2 has a Programmable Counter Array, an XRAM of 256 or
768 bytes, a Hardware Watchdog Timer, a more versatile serial channel that
C) and Industrial (-40 to 85
Rev. 4188F–8051–01/08

TS80C51RA2-VCA Summary of contents

  • Page 1

    ... In addition, the TS80C51Rx2 has a Programmable Counter Array, an XRAM of 256 or 768 bytes, a Hardware Watchdog Timer, a more versatile serial channel that C) and Industrial (- High Performance 8-bit Microcontroller TS80C51RA2 TS83C51RB2 TS83C51RC2 TS83C51RD2 TS87C51RB2 TS87C51RC2 TS87C51RD2 AT80C51RA2 AT83C51RB2 AT83C51RC2 AT83C51RD2 ...

  • Page 2

    ... In the idle mode the CPU is frozen while the timers, the serial port and the interrupt system are still operating. In the power-down mode the RAM is saved and all other functions are inoperative. PDIL40 PLCC44 VQFP44 1.4 TS80C51RA2 TS80C51RD2 TS83C51RB2 TS83C51RC2 TS83C51RD2 TS87C51RB2 ...

  • Page 3

    Block Diagram XTAL1 XTAL2 ALE/ PROG PSEN EA/VPP (3) RD (3) WR 4188F–8051–01/08 (3) (3) ROM RAM /EPROM EUART 256x8 0/16/32/64Kx8 C51 IB-bus CORE CPU Timer 0 Parallel I/O Ports & Ext. Bus INT Timer 1 Ctrl Port 0 ...

  • Page 4

    SFR Mapping The Special Function Registers (SFRs) of the TS80C51Rx2 fall into the following categories: • C51 core registers: ACC, B, DPH, DPL, PSW, SP, AUXR1 • I/O port registers: P0, P1, P2, P3, P4, P5 • Timer registers: ...

  • Page 5

    Table 4-1. Bit Non Bit addressable addressable 0/8 1/9 CH F8h 0000 0000 B F0h 0000 0000 P5 bit CL addressable E8h 0000 0000 1111 1111 ACC E0h 0000 0000 CCON CMOD D8h 00X0 0000 00XX X000 PSW D0h 0000 ...

  • Page 6

    Pin Configuration P1 P1.1 / T2EX P1.2 3 P1.3 4 P1.4 5 P1 P1.7 RST 9 P3.0/RxD 10 PDIL/ P3.1/TxD 11 12 P3.2/INT0 CDIL40 P3.3/INT1 13 14 P3.4/T0 15 P3.5/T1 P3.6/WR ...

  • Page 7

    P5.5 P0.3/AD3 P0.2/AD2 P5.6 P0.1/AD1 P0.0/AD0 P5.7 VCC NIC P1.0/T2 P4.0 P1.1/T2EX P1.2 P1.3 P4.1 P1.4 P4.2 P5.5 P0.3/AD3 P0.2/AD2 P5.6 P0.1/AD1 P0.0/AD0 P5.7 VCC VSS P1.0/T2 P4.0 P1.1/T2EX P1.2 P1.3 P4.1 P1.4 NIC: No InternalConnection 4188F–8051–01/ ...

  • Page 8

    Pin Number Mnemonic DIL LCC VQFP 1 Vss1 P0.0-P0.7 39-32 43-36 P1.0-P1.7 1-8 2 P2.0-P2.7 ...

  • Page 9

    Pin Number Mnemonic DIL LCC VQFP 1 Reset 9 10 ALE/PROG 30 33 PSEN XTAL1 19 21 XTAL2 18 20 5.1 Pin ...

  • Page 10

    P0.0 P0.1 P0.2 P0.3 P0.4 P0.5 P0.6 P0.7 P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7 P2.0 P2.1 P2.2 P2.3 P2.4 P2.5 P2.6 P2.7 P3.0 P3.1 P3.2 P3.3 P3.4 P3.5 P3.6 P3.7 RESET ALE/PROG AT/TS8xC51Rx2 ...

  • Page 11

    PSEN EA/VPP XTAL1 XTAL2 P4.0 P4.1 P4.2 P4.3 P4.4 P4.5 P4.6 P4.7 P5.0 P5.1 P5.2 P5.3 P5.4 P5.5 P5.6 P5.7 4188F–8051–01/08 AT/TS8xC51Rx2 ...

  • Page 12

    TS80C51Rx2 Enhanced Features In comparison to the original 80C52, the TS8xC51Rx2 implements some new features, which are : • The X2 option. • The Dual Data Pointer. • The extended RAM. • The Programmable Counter Array (PCA). • The ...

  • Page 13

    Figure 5-1. Mode Switching Waveforms Figure 5-2. XTAL1 XTAL1:2 X2 bit CPU clock STD Mode The X2 bit in the CKCON register tion to 6 clock cycles and vice versa. At reset, the standard speed is activated (STD mode). Setting ...

  • Page 14

    ... Bit Number Reset Value = XXXX XXX0b Not bit addressable For further details on the X2 feature, please refer to ANM072 available on the web (http://www.atmel.com) AT/TS8xC51Rx2 14 Bit Mnemonic Description Reserved - The value read from this bit is indeterminate. Do not set this bit. Reserved - The value read from this bit is indeterminate. Do not set this bit. ...

  • Page 15

    Dual Data Pointer Register The additional data pointer can be used to speed up code execution and reduce code size in a number of ways. The dual DPTR structure is a way by which the chip will specify the ...

  • Page 16

    Application Software can take advantage of the additional data pointers to both increase speed and reduce code size, for example, block operations (copy, compare, search ...) are well served by using one data pointer as a ’source’ pointer and ...

  • Page 17

    Expanded RAM (XRAM) The TS80C51Rx2 provide additional Bytes of ramdom access memory (RAM) space for increased data parameter handling and high level language usage. RA2, RB2 and RC2 devices have 256 bytes of expanded RAM, from 00H to FFH ...

  • Page 18

    MOVX @ Ri and MOVX @DPTR will generate either read or write signals on P3.6 (WR) and P3.7 (RD). The stack pointer (SP) may be located anywhere in the 256 bytes RAM (lower and upper ...

  • Page 19

    ... Auto-reload Mode The auto-reload mode configures timer 16-bit timer or event counter with automatic reload. If DCEN bit in T2MOD is cleared, timer 2 behaves as in 80C52 (refer to the Atmel 8-bit Microcontroller Hardware description). If DCEN bit is set, timer 2 acts as an Up/down timer/counter as shown in Figure 6-2. In this mode the T2EX pin controls the direction of count. ...

  • Page 20

    Auto-reload Mode Up/Down Counter (DCEN = 1) Figure 6-2. XTAL1 F XTAL 6.2.2 Programmable Clock-Output In the clock-out mode, timer 2 operates as a 50%-duty-cycle, programmable clock generator (See Figure 6-3) . The input clock increments TL2 at frequency F ...

  • Page 21

    It is possible to use timer baud rate generator and a clock generator simultaneously. For this configuration, the baud rates and clock frequencies are not independent since both func- tions use the values in the RCAP2H and ...

  • Page 22

    Bit Number Reset Value = 0000 0000b Bit addressable Table 6- AT/TS8xC51Rx2 22 Bit Mnemonic Description Timer 2 overflow Flag TF2 Must be cleared by software. Set by hardware on ...

  • Page 23

    Bit Number Reset Value = XXXX XX00b Not bit addressable 4188F–8051–01/08 Bit Mnemonic Description Reserved - The value read from this bit is indeterminate. Do not set this bit. Reserved - The ...

  • Page 24

    Programmable Counter Array PCA The PCA provides more timing capabilities with less CPU intervention than the standard timer/counters. Its advantages include reduced software overhead and improved accuracy. The PCA consists of a dedicated timer/counter which serves as the time ...

  • Page 25

    PCA Timer/Counter Figure 6-4. Fosc /12 Fosc / 4 T0 OVF P1.2 Idle Table 6-4. Symbol CIDL WDTE - CPS1 CPS0 ECF 1. 2. The CMOD SFR includes three additional bits associated with the PCA (See Figure 6-4 and Table ...

  • Page 26

    The CIDL bit which allows the PCA to stop during idle mode. • The WDTE bit which enables or disables the watchdog function on module 4. • The ECF bit which when set causes an interrupt and the PCA ...

  • Page 27

    PCA Interrupt System Figure 6-5. PCA Timer/Counter Module 0 Module 1 Module 2 Module 3 Module 4 CMOD.0 ECF PCA Modules: each one of the five compare/capture modules has six possible functions. It can perform: • 16-bit Capture, positive-edge triggered, ...

  • Page 28

    The last bit in the register ECOM (CCAPMn.6) when set enables the comparator function. Table 6-7 shows the CCAPMn settings for the various PCA functions. . Table 6-6. CCAPMn Address Symbol - ECOMn CAPPn ...

  • Page 29

    There are two additional registers associated with each of the PCA modules. They are CCAPnH and CCAPnL and these are the registers that store the 16-bit count when a capture occurs or a compare should occur. When a module is ...

  • Page 30

    PCA Capture Mode Figure 6- Cex.n ECOMn 6.3.2 16-bit Software Timer/ Compare Mode The PCA modules can be used as software timers by setting both the ECOM and MAT bits in the modules CCAPMn register. The PCA timer ...

  • Page 31

    PCA Compare Mode and PCA Watchdog Timer Figure 6-7. Write to CCAPnL Reset Write to CCAPnH Enable Only for Module 4 Before enabling ECOM bit, CCAPnL and CCAPnH should be set with a non zero value, other- ...

  • Page 32

    PCA High Speed Output Mode Figure 6-8. Write to Reset CCAPnL Write to CCAPnH 0 Enable 1 Before enabling ECOM bit, CCAPnL and CCAPnH should be set with a non zero value, other- wise an unwanted match could happen. Once ...

  • Page 33

    Figure 6-9. 6.3.5 PCA Watchdog Timer An on-board watchdog timer is available with the PCA to improve the reliability of the system without increasing chip count. Watchdog timers are useful for systems that are susceptible to noise, power glitches, or ...

  • Page 34

    TS80C51Rx2 Serial I/O Port The serial I/O port in the TS80C51Rx2 is compatible with the serial I/O port in the 80C52. It provides both synchronous and asynchronous communication modes. It operates as an Uni- versal Asynchronous Receiver and Transmitter ...

  • Page 35

    Figure 6-12. UART Timings in Modes 2 and 3 SMOD0=0 SMOD0=1 SMOD0=1 6.4.2 Automatic Address Recognition The automatic address recognition feature is enabled when the multiprocessor communication feature is enabled (SM2 bit in SCON register is set). Implemented in hardware, ...

  • Page 36

    Slave C:SADDR1111 0010b The SADEN byte is selected so that each slave may be addressed separately. For slave A, bit 0 (the LSB don’t-care bit; for slaves B and C, bit communicate with ...

  • Page 37

    Table 6-12. 7 Reset Value = 0000 0000b Not bit addressable Table 6-13. 7 Reset Value = 0000 0000b Not bit addressable Table 6-14. 7 FE/SM0 4188F–8051–01/08 SADEN - Slave Address Mask Register (B9h SADDR - Slave ...

  • Page 38

    Bit Number Reset Value = 0000 0000b Bit addressable Table 6-15. 7 SMOD1 AT/TS8xC51Rx2 38 Bit Mnemonic Description Framing Error bit (SMOD0=1) Clear to reset the error state, not cleared by a ...

  • Page 39

    Bit Number Reset Value = 00X1 0000b Not bit addressable Power-off flag reset value will be 1 only after a power on (cold reset). A warm reset doesn’t affect the value of ...

  • Page 40

    Interrupt System The TS80C51Rx2 has a total of 7 interrupt vectors: two external interrupts (INT0 and INT1), three timer interrupts (timers 0, 1 and 2), the serial port interrupt and the PCA global interrupt. These interrupts are shown in ...

  • Page 41

    Table 6-16. IPH low-priority interrupt can be interrupted by a high priority interrupt, but not by another low-prior- ity interrupt. A high-priority interrupt can’t be interrupted by any other interrupt source. If two interrupt requests ...

  • Page 42

    Table 6-18 Bit Number Reset Value = X000 0000b Bit addressable AT/TS8xC51Rx2 42 IP Register IP - Interrupt Priority Register (B8h PPC PT2 PS Bit Mnemonic Description ...

  • Page 43

    Table 6-19 Bit Number Reset Value = X000 0000b Not bit addressable 4188F–8051–01/08 IPH Register IPH - Interrupt Priority High Register (B7h PPCH PT2H PSH Bit Mnemonic ...

  • Page 44

    Idle Mode An instruction that sets PCON.0 causes that to be the last instruction executed before going into the Idle mode. In the Idle mode, the internal clock signal is gated off to the CPU, but not to the ...

  • Page 45

    Figure 6-14. Power-Down Exit Waveform INT0 INT1 XTAL1 Active phase Exit from power-down by reset redefines all the SFRs, exit from power-down by external inter- rupt does no affect the SFRs. Exit from power-down by either reset or external interrupt ...

  • Page 46

    Hardware Watchdog Timer The WDT is intended as a recovery method in situations where the CPU may be subjected to software upset. The WDT consists of a 14-bit counter and the WatchDog Timer ReSeT (WDTRST) SFR. The WDT is ...

  • Page 47

    Bit Number Reset value XXXX X000 6.8.2 WDT during Power-down and Idle In Power-down mode the oscillator stops, which means the WDT also stops. While in Power- down mode the user does ...

  • Page 48

    TM 6.9 ONCE Mode (ON Chip Emulation) The ONCE mode facilitates testing and debugging of systems using TS8xC51Rx2 without removing the circuit from the board. The ONCE mode is invoked by driving certain pins of the TS80C51Rx2; the following sequence ...

  • Page 49

    Power-Off Flag The power-off flag allows the user to distinguish between a “cold start” reset and a “warm start” reset. A cold start reset is the one induced by V applied to the device and could be generated for ...

  • Page 50

    Reduced EMI Mode The ALE signal is used to demultiplex address and data buses on port 0 when used with exter- nal program or data memory. Nevertheless, during internal code execution, ALE signal is still generated. In order to ...

  • Page 51

    TS83C51RB2/RC2/RD2 ROM 8.1 ROM Structure The TS83C51RB2/RC2/RD2 ROM memory is divided in three different arrays: • the code array:16/32/64 Kbytes. • the encryption array:64 bytes. • the signature array:4 bytes. 8.2 ROM Lock System The program Lock system, when ...

  • Page 52

    Verify Algorithm Refer to Section “Verify algorithm”. AT/TS8xC51Rx2 52 4188F–8051–01/08 ...

  • Page 53

    TS87C51RB2/RC2/RD2 EPROM 9.1 EPROM Structure The TS87C51RB2/RC2/RD2 EPROM is divided in two different arrays: • the code array:16/32/64 Kbytes. • the encryption array:64 bytes. In addition a third non programmable array is implemented: • the signature array: 4 bytes. ...

  • Page 54

    WARNING: Security level 2 and 3 should only be programmed after EPROM and Core verification. 9.2.3 Signature bytes The TS87C51RB2/RC2/RD2 contains 4 factory programmed signatures bytes. To read these bytes, perform the process described in Section “Signature bytes”. 9.3 EPROM ...

  • Page 55

    Figure 9-1. PROGRAM SIGNALS* CONTROL SIGNALS MHz * See Table 31. for proper value on these inputs 9.3.3 Programming Algorithm The Improved Quick Pulse algorithm is based on the Quick Pulse algorithm and decreases the number of ...

  • Page 56

    ... Exposing the EPROM to an ultraviolet lamp of 12,000 µW/cm has four signature bytes in location 30h, 31h, 60h and 61h. To Signature Bytes Content Location Contents 30h 58h 31h 57h 60h 7Ch Read/Verify Cycle Data Out Comment Manufacturer Code: Atmel Family Code: C51 X2 Product name: TS83C51RD2 2 rat- 4188F–8051–01/08 ...

  • Page 57

    FCh 60h 37h 60h B7h 60h 3Bh 60h BBh 61h FFh AT/TS8xC51Rx2 Product name: TS87C51RD2 Product name: TS83C51RC2 Product name: TS87C51RC2 Product name: TS83C51RB2 Product name: TS87C51RB2 Product revision number 57 ...

  • Page 58

    ... CPU was running under reset. In Atmel new devices, the CPU is no more active during reset, so the power consumption is very low but is not really representative of what will happen in the customer system. That’s why, while ...

  • Page 59

    DC Parameters in Standard Voltage Table 11-1. Symbol Parameter V Output High Voltage, ports Output High Voltage, port 0 OH1 V Output High Voltage,ALE, PSEN OH2 R RST Pulldown Resistor RST I Logical ...

  • Page 60

    DC Parameters for Low Voltage T = 0°C to +70° -40°C to +85° Parameters for Low Voltage Table 11-2. Symbol Parameter V Input Low Voltage IL V Input High Voltage except XTAL1, ...

  • Page 61

    Capacitance loading on Ports 0 and 2 may cause spurious noise pulses to be superimposed on the V and 3. The noise is due to external bus capacitance discharging into the Port 0 and Port 2 pins when these ...

  • Page 62

    Figure 11-3. I Figure 11-4. I Reset = Vss after a high pulse during at least 24 clock cycles Figure 11-5. Clock Signal Waveform for I 11.5 AC Parameters 11.5.1 Explanation of the AC Symbols Each timing symbol has 5 ...

  • Page 63

    +70°C (commercial temperature range -40°C to +85°C (industrial temperature range Table 11-3. gives the maximum applicable load capacitance for Port 0, Port 1, 2 and 3, and ALE and PSEN ...

  • Page 64

    External Program Memory Characteristics Table 11-5. Symbol T T LHLL T AVLL T LLAX T LLIV T LLPL T PLPH T PLIV T PXIX T PXIZ T PXAV T AVIV T PLAZ Table 11-6. Speed Symbol T T LHLL ...

  • Page 65

    Table 11-7. Symbol PLPH 11.5.3 External Program Memory Read Cycle Figure 11-6. External Program Memory Read Cycle ALE PSEN PORT 0 INSTR IN ADDRESS PORT 2 OR SFR-P2 4188F–8051–01/08 ...

  • Page 66

    External Data Memory Characteristics Symbol T RLRH T WLWH T RLDV T RHDX T RHDZ T LLDV T AVDV T LLWL T AVWL T QVWX T QVWH T WHQX T RLAZ T WHLH Table 11-8. Speed -M 40 MHz ...

  • Page 67

    Table 11-9. Symbol T RLRH T WLWH T RLDV T RHDX T RHDZ T T AVDV AVWL T QVWX T QVWH T WHQX T T WHLH T WHLH 11.5.5 External Data Memory Write Cycle Figure 11-7. External ...

  • Page 68

    Figure 11-8. External Data Memory Read Cycle ALE PSEN RD PORT 0 ADDRESS PORT 2 OR SFR-P2 11.5.7 Serial Port Timing - Shift Register Mode Symbol T XLXL T QVHX T XHQX T XHDX T XHDV Table 11-10. AC Parameters ...

  • Page 69

    Table 11-11. AC Parameters for a Variable Clock: derating formula Symbol T T QVHX T XHQX T XHDX T XHDV 11.5.8 Shift Register Timing Waveforms Figure 11-9. Shift Register Timing Waveforms 0 INSTRUCTION ALE CLOCK T QVXH OUTPUT DATA WRITE ...

  • Page 70

    EPROM Programming and Verification Characteristics T = 21°C to 27° Symbol 1/T CLCL T AVGL T GHAX T DVGL T GHDX T EHSH T SHGL T GHSL T GLGH T AVQV T ELQV ...

  • Page 71

    External Clock Drive Characteristics (XTAL1) Symbol Parameter T Oscillator Period CLCL T High Time CHCX T Low Time CLCX T Rise Time CLCH T Fall Time CHCL T /T Cyclic ratio in X2 mode CHCX CLCX 11.5.12 External Clock ...

  • Page 72

    Clock Waveforms Valid in normal clock mode mode XTAL2 signal must be changed to XTAL2 divided by two. Figure 11-14. Clock Waveforms STATE4 INTERNAL CLOCK P1P2 XTAL2 ALE EXTERNAL PROGRAM MEMORY FETCH PSEN PCL OUT DATA P0 ...

  • Page 73

    ... Ordering Information Part Number Memory size TS80C51RA2-MCA TS80C51RA2-MCB TS80C51RA2-MCE TS80C51RA2-MIA TS80C51RA2-MIB TS80C51RA2-MIE TS80C51RA2-LCA TS80C51RA2-LCB TS80C51RA2-LCE TS80C51RA2-LIA TS80C51RA2-LIB TS80C51RA2-LIE TS80C51RA2-VCA TS80C51RA2-VCB TS80C51RA2-VCE TS80C51RA2-VIA TS80C51RA2-VIB TS80C51RA2-VIE AT80C51RA2-3CSUM Romless AT80C51RA2-SLSUM Romless AT80C51RA2-RLTUM Romless AT80C51RA2-3CSIM AT80C51RA2-SLSIM AT80C51RA2-RLTIM AT80C51RA2-3CSCL AT80C51RA2-SLSCL AT80C51RA2-RLTCL AT80C51RA2-3CSUL Romless AT80C51RA2-SLSUL Romless AT80C51RA2-RLTUL Romless 4188F– ...

  • Page 74

    Part Number Memory size AT80C51RA2-3CSCV AT80C51RA2-SLSCV AT80C51RA2-RLTCV AT80C51RA2-3CSIV AT80C51RA2-SLSIV AT80C51RA2-RLSIV TS80C51RD2-MCA Not recommended use AT87C51RD2 TS80C51RD2-MCB Not recommended use AT87C51RD2 TS80C51RD2-MCE Not recommended use AT87C51RD2 TS80C51RD2-MIA Not recommended use AT87C51RD2 TS80C51RD2-MIB Not recommended use AT87C51RD2 TS80C51RD2-MIE Not recommended use AT87C51RD2 ...

  • Page 75

    Part Number Memory size TS87C51RB2-MCA TS87C51RB2-MCB TS87C51RB2-MCE TS87C51RB2-MIA TS87C51RB2-MIB TS87C51RB2-MIE TS87C51RB2-LCA TS87C51RB2-LCB TS87C51RB2-LCE TS87C51RB2-LIA TS87C51RB2-LIB TS87C51RB2-LIE TS87C51RB2-VCA TS87C51RB2-VCB TS87C51RB2-VCE TS87C51RB2-VIA TS87C51RB2-VIB TS87C51RB2-VIE AT87C51RB2-3CSUM OTP 16k Bytes AT87C51RB2-SLSUM OTP 16k Bytes AT87C51RB2-RLTUM OTP 16k Bytes AT87C51RB2-3CSUL OTP 16k Bytes AT87C51RB2-SLSUL OTP ...

  • Page 76

    Part Number Memory size TS87C51RC2-MCA TS87C51RC2-MCB TS87C51RC2-MCE TS87C51RC2-MIA TS87C51RC2-MIB TS87C51RC2-MIE TS87C51RC2-LCA TS87C51RC2-LCB TS87C51RC2-LCE TS87C51RC2-LIA TS87C51RC2-LIB TS87C51RC2-LIE TS87C51RC2-VCA TS87C51RC2-VCB TS87C51RC2-VCE TS87C51RC2-VIA TS87C51RC2-VIB TS87C51RC2-VIE AT87C51RC2-3CSUM OTP 32k Bytes AT87C51RC2-SLSUM OTP 32k Bytes AT87C51RC2-RLTUM OTP 32k Bytes AT87C51RC2-3CSUL OTP 32k Bytes AT87C51RC2-SLSUL OTP ...

  • Page 77

    Part Number Memory size TS87C51RD2-MCA TS87C51RD2-MCB TS87C51RD2-MCE TS87C51RD2-MIA TS87C51RD2-MIB TS87C51RD2-MIE TS87C51RD2-LCA TS87C51RD2-LCB TS87C51RD2-LCE TS87C51RD2-LIA TS87C51RD2-LIB TS87C51RD2-LIE TS87C51RD2-VCA TS87C51RD2-VCB TS87C51RD2-VCE TS87C51RD2-VCL TS87C51RD2-VIA TS87C51RD2-VIB TS87C51RD2-VIE AT87C51RD2-3CSUM OTP 64k Bytes AT87C51RD2-SLSUM OTP 64k Bytes AT87C51RD2-RLTUM OTP 64k Bytes AT87C51RD2-3CSUL OTP 64k Bytes AT87C51RD2-SLSUL ...

  • Page 78

    Part Number Memory size TS83C51RB2-MCA TS83C51RB2-MCB TS83C51RB2-MCE TS83C51RB2-MIA TS83C51RB2-MIB TS83C51RB2-MIE TS83C51RB2-LCA TS83C51RB2-LCB TS83C51RB2-LCE TS83C51RB2-LIA TS83C51RB2-LIB TS83C51RB2-LIE TS83C51RB2-VCA TS83C51RB2-VCB TS83C51RB2-VCE TS83C51RB2-VIA TS83C51RB2-VIB TS83C51RB2-VIE AT83C51RB2-3CSUM ROM 32k Bytes AT83C51RB2-SLSUM ROM 32k Bytes AT83C51RB2-RLTUM ROM 32k Bytes AT83C51RB2-3CSUL ROM 32k Bytes AT83C51RB2-SLSUL ROM ...

  • Page 79

    Part Number Memory size TS83C51RC2-MCA TS83C51RC2-MCB TS83C51RC2-MCE TS83C51RC2-MIA TS83C51RC2-MIB TS83C51RC2-MIE TS83C51RC2-LCA TS83C51RC2-LCB TS83C51RC2-LCE TS83C51RC2-LIA TS83C51RC2-LIB TS83C51RC2-LIE TS83C51RC2-VCA TS83C51RC2-VCB TS83C51RC2-VCE TS83C51RC2-VIA TS83C51RC2-VIB TS83C51RC2-VIE AT83C51RC2-3CSUM ROM 32k Bytes AT83C51RC2-SLSUM ROM 32k Bytes AT83C51RC2-RLTUM ROM 32k Bytes AT83C51RC2-3CSUL ROM 32k Bytes AT83C51RC2-SLSUL ROM ...

  • Page 80

    Part Number Memory size TS83C51RD2-MCA TS83C51RD2-MCB TS83C51RD2-MCE TS83C51RD2-MIA TS83C51RD2-MIB TS83C51RD2-MIE TS83C51RD2-LCB TS83C51RD2-LCE TS83C51RD2-LIA TS83C51RD2-LIB TS83C51RD2-LIE TS83C51RD2-VCA TS83C51RD2-VCB TS83C51RD2-VCE TS83C51RD2-VIA TS83C51RD2-VIB TS83C51RD2-VIE AT83C51RD2-3CSUM ROM 64k Bytes AT83C51RD2-SLSUM ROM 64k Bytes AT83C51RD2-RLTUM ROM 64k Bytes AT83C51RD2-3CSUL ROM 64k Bytes AT83C51RD2-SLSUL ROM 64k ...

  • Page 81

    Package Drawings 13.1 PLCC44 4188F–8051–01/08 AT/TS8xC51Rx2 81 ...

  • Page 82

    PDIL40 AT/TS8xC51Rx2 82 4188F–8051–01/08 ...

  • Page 83

    VQFP44 4188F–8051–01/08 AT/TS8xC51Rx2 83 ...

  • Page 84

    VQFP64 AT/TS8xC51Rx2 84 4188F–8051–01/08 ...

  • Page 85

    PLCC68 14. Datasheet Revision History 14.1 Changes from 4188E to 4188F 1. Removed TS80C51RD2 and AT80C51RD2 from 2. Removed non-green part numbers from ordering information. 4188F–8051–01/08 AT/TS8xC51Rx2 “Ordering Information” on page 73. 85 ...

  • Page 86

    ... Disclaimer: The information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise, to any intellectual property right is granted by this document or in connection with the sale of Atmel products. EXCEPT AS SET FORTH IN ATMEL’S TERMS AND CONDI- TIONS OF SALE LOCATED ON ATMEL’S WEB SITE, ATMEL ASSUMES NO LIABILITY WHATSOEVER AND DISCLAIMS ANY EXPRESS, IMPLIED OR STATUTORY WARRANTY RELATING TO ITS PRODUCTS INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT ...