TS80C51RA2-VCB Atmel, TS80C51RA2-VCB Datasheet
TS80C51RA2-VCB
Specifications of TS80C51RA2-VCB
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TS80C51RA2-VCB Summary of contents
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... Programmable Counter Array with High Speed Output, Compare / Capture, Pulse Width Modulator, Watchdog Timer Capabilities Rev March, 2001 TS80C51RA2/RD2 TS83C51RB2/RC2/RD2 TS87C51RB2/RC2/RD2 The fully static design of the TS80C51Rx2 allows to reduce system power consumption by bringing the clock frequency down to any value, even DC, without loss of data ...
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... TS80C51RA2/RD2 TS83C51RB2/RC2/RD2 TS87C51RB2/RC2/RD2 PDIL40 PLCC44 ROM (bytes) VQFP44 1.4 TS80C51RA2 0 TS80C51RD2 0 TS83C51RB2 16k TS83C51RC2 32k TS83C51RD2 64k TS87C51RB2 0 TS87C51RC2 0 TS87C51RD2 0 PLCC68 ROM (bytes) VQFP64 1.4 TS80C51RD2 0 TS83C51RD2 64k TS87C51RD2 0 3. Block Diagram (3) XTAL1 XTAL2 ALE/ PROG PSEN CPU EA/V PP (3) RD (3) ...
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... RCAP2H TL2 0000 0000 0000 0000 AUXR1 TL0 TL1 TH0 0000 0000 0000 0000 DPL DPH 0000 0000 2/A 3/B 4/C TS80C51RA2/RD2 TS83C51RB2/RC2/RD2 TS87C51RB2/RC2/RD2 5/D 6/E 7/F CCAPL3H CCAPL4H XXXX XXXX XXXX XXXX CCAPL3L CCAPL4L XXXX XXXX XXXX XXXX CCAPM3 CCAPM4 ...
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... TS80C51RA2/RD2 TS83C51RB2/RC2/RD2 TS87C51RB2/RC2/RD2 5. Pin Configuration P1 VCC 39 P0 P1.1 / T2EX P1.2 3 P1 P1 P1.6 P0 P1.7 P0 RST 9 32 EA/VPP P3.0/RxD 10 31 PDIL/ ALE/PROG P3.1/TxD PSEN CDIL40 P3.2/INT0 29 P3.3/INT1 P2.7 / A15 13 28 P2.6 / A14 27 P3.4/T0 14 P2.5 / A13 15 26 P3.5/T1 P2.4 / A12 P3 ...
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... VSS 9 VQFP64 TS80C51RA2/RD2 TS83C51RB2/RC2/RD2 TS87C51RB2/RC2/RD2 P5.0 59 P2.4/A12 58 P2.3/A11 57 P4.7 56 P2.2/A10 55 P2.1/A9 54 P2.0/A8 P4.6 53 NIC 52 51 VSS 50 P4.5 49 XTAL1 48 XTAL2 47 P3.7/RD 46 P4.4 45 P3.6/ P2.4/A12 P2.3/A11 P4.7 P2.2/A10 P2.1/A9 P2.0/A8 P4.6 NIC VSS P4.5 XTAL1 XTAL2 P3.7/RD P4.4 P3 ...
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... TS80C51RA2/RD2 TS83C51RB2/RC2/RD2 TS87C51RB2/RC2/RD2 Pin Number Mnemonic DIL LCC VQFP 1 Vss1 P0.0-P0.7 39-32 43-36 37-30 P1.0-P1.7 1-8 2-9 40-44 1 P2.0-P2.7 21-28 24-31 18-25 P3.0-P3.7 10-17 11, 5, 13-19 7- Type Name And Function I Ground: 0V reference I Optional Ground: Contact the Sales Office for ground connection. ...
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... Reset: A high on this pin for two machine cycles while the oscillator is running, resets the device. An internal diffused resistor to V using only an external capacitor to V time-out, the reset pin becomes an output during the time the internal reset is activated. TS80C51RA2/RD2 permits a power-on reset SS If the hardware watchdog reaches its CC. ...
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... TS80C51RA2/RD2 TS83C51RB2/RC2/RD2 TS87C51RB2/RC2/RD2 Pin Number Mnemonic ALE/PROG PSEN EA XTAL1 XTAL2 Type Name And Function O (I) Address Latch Enable/Program Pulse: Output pulse for latching the low byte of the address during an access to external memory. In normal operation, ALE is emitted at a constant rate of 1/6 (1 mode) the oscillator frequency, and can be used for external timing or clocking ...
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... Table 2. 64/68 Pin Packages Configuration VSS VCC P0.0 P0.1 P0.2 P0.3 P0.4 P0.5 P0.6 P0.7 P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7 P2.0 P2.1 P2.2 P2.3 P2.4 P2.5 P2.6 P2.7 P3.0 P3.1 Rev March, 2001 TS80C51RA2/RD2 TS83C51RB2/RC2/RD2 TS87C51RB2/RC2/RD2 SQUARE VQFP64 PLCC68 1 ...
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... TS80C51RA2/RD2 TS83C51RB2/RC2/RD2 TS87C51RB2/RC2/RD2 P3.2 P3.3 P3.4 P3.5 P3.6 P3.7 RESET ALE/PROG PSEN EA/VPP XTAL1 XTAL2 P4.0 P4.1 P4.2 P4.3 P4.4 P4.5 P4.6 P4.7 P5.0 P5.1 P5.2 P5.3 P5.4 P5.5 P5.6 P5.7 10 SQUARE VQFP64 PLCC68 1 Rev March, 2001 ...
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... X2 bit is validated on XTAL1 2 rising edge to avoid glitches when switching from X2 to STD mode. Figure 2. shows the mode switching waveforms. XTAL1:2 2 XTAL1 F XTAL Rev March, 2001 state machine: 6 clock cycles. 0 CPU control 1 F OSC X2 CKCON reg Figure 1. Clock Generation Diagram TS80C51RA2/RD2 TS83C51RB2/RC2/RD2 TS87C51RB2/RC2/RD2 : 11 ...
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... TS80C51RA2/RD2 TS83C51RB2/RC2/RD2 TS87C51RB2/RC2/RD2 XTAL1 XTAL1:2 X2 bit CPU clock STD Mode The X2 bit in the CKCON register (See Table 3.) allows to switch from 12 clock cycles per instruction to 6 clock cycles and vice versa. At reset, the standard speed is activated (STD mode). Setting this bit activates the X2 feature (X2 mode) ...
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... X2 Set to select 6 clock periods per machine cycle (X2 mode, F Reset Value = XXXX XXX0b Not bit addressable For further details on the X2 feature, please refer to ANM072 available on the web (http://www.atmel-wm.com) Rev March, 2001 Table 3. CKCON Register Description TS80C51RA2/RD2 TS83C51RB2/RC2/RD2 TS87C51RB2/RC2/RD2 2). OSC XTAL =F ) ...
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... TS80C51RA2/RD2 TS83C51RB2/RC2/RD2 TS87C51RB2/RC2/RD2 6.2. Dual Data Pointer Register Ddptr The additional data pointer can be used to speed up code execution and reduce code size in a number of ways. The dual DPTR structure is a way by which the chip will specify the address of an external data memory location ...
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... In other words, the block move routine works the same whether DPS is '0' or '1' on entry. Observe that without the last instruction (INC AUXR1), the routine will exit with DPS in the opposite state. Rev March, 2001 TS80C51RA2/RD2 TS83C51RB2/RC2/RD2 TS87C51RB2/RC2/RD2 ; address of SOURCE ...
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... TS80C51RA2/RD2 TS83C51RB2/RC2/RD2 TS87C51RB2/RC2/RD2 6.3. Expanded RAM (XRAM) The TS80C51Rx2 provide additional Bytes of ramdom access memory (RAM) space for increased data parameter handling and high level language usage. RA2, RB2 and RC2 devices have 256 bytes of expanded RAM, from 00H to FFH in external data space; ...
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... X2 mode is used) 1 ALE is active only during a MOVX or MOVC instruction Internal/External RAM (00H-FFH) access using MOVX @ Ri/ @ DPTR EXTRAM Operating Mode 0 Internal XRAM access using MOVX @ Ri/ @ DPTR 1 External data memory access TS80C51RA2/RD2 TS83C51RB2/RC2/RD2 TS87C51RB2/RC2/RD2 FFFF Special External Data Register Memory 0000 EXTRA ...
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... TS80C51RA2/RD2 TS83C51RB2/RC2/RD2 TS87C51RB2/RC2/RD2 6.4. Timer 2 TS80C51RX2 The timer 2 in the 16-bit timer/counter: the count is maintained by two eight-bit timer registers, TH2 and TL2, connected in cascade controlled by T2CON register (See Table 6) and T2MOD register (See Table 7). Timer 2 operation is similar to Timer 0 and Timer 1. C/T2 selects F as the timer clock input ...
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... RCAP2L RCAP2H (8-bit) (8-bit) (UP COUNTING RELOAD VALUE) /2. The timer repeatedly counts to overflow from a loaded value. OSC F osc = -------------------------------------------------------------------------------------- 4 65536 RCAP2H – RCAP2L TS80C51RA2/RD2 TR2 T2CONreg T2EX: if DCEN=1, 1=UP if DCEN=1, 0=DOWN if DCEN = 0, up counting TOGGLE T2CONreg EXF2 TIMER 2 TF2 INTERRUPT T2CONreg 19 ...
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... TS80C51RA2/RD2 TS83C51RB2/RC2/RD2 TS87C51RB2/RC2/RD2 It is possible to use timer baud rate generator and a clock generator simultaneously. For this configuration, the baud rates and clock frequencies are not independent since both functions use the values in the RCAP2H and RCAP2L registers. XTAL1 (: mode) T2 T2EX 20 :2 TR2 ...
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... If RCLK=1 or TCLK=1, CP/RL2# is ignored and timer is forced to auto-reload on timer 2 overflow. 0 CP/RL2# Clear to auto-reload on timer 2 overflows or negative transitions on T2EX pin if EXEN2=1. Set to capture on negative transitions on T2EX pin if EXEN2=1. Reset Value = 0000 0000b Bit addressable Rev March, 2001 Table 6. T2CON Register TCLK EXEN2 Description TS80C51RA2/RD2 TS83C51RB2/RC2/RD2 TS87C51RB2/RC2/RD2 TR2 C/T2# CP/RL2# ). OSC 21 ...
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... TS80C51RA2/RD2 TS83C51RB2/RC2/RD2 TS87C51RB2/RC2/RD2 T2MOD - Timer 2 Mode Control Register (C9h Bit Bit Number Mnemonic Reserved 7 - The value read from this bit is indeterminate. Do not set this bit. Reserved 6 - The value read from this bit is indeterminate. Do not set this bit. Reserved 5 - The value read from this bit is indeterminate. Do not set this bit. ...
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... X2 mode mode) PCA component External I/O Pin 16-bit Counter P1.2 / ECI 16-bit Module 0 P1.3 / CEX0 16-bit Module 1 P1.4 / CEX1 16-bit Module 2 P1.5 / CEX2 16-bit Module 3 P1.6 / CEX3 16-bit Module 4 P1.7 / CEX4 See Figure 7) TS80C51RA2/RD2 TS83C51RB2/RC2/RD2 TS87C51RB2/RC2/RD2 . The timer count source is 23 ...
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... TS80C51RA2/RD2 TS83C51RB2/RC2/RD2 TS87C51RB2/RC2/RD2 Fosc /12 Fosc / 4 T0 OVF P1.2 CIDL Idle CF Table 8. CMOD: PCA Counter Mode Register CMOD Address 0D9H Reset value Symbol CIDL WDTE - CPS1 CPS0 ECF a. User software should not write 1s to reserved bits. These bits may be used in future 8051 family products to invoke new features ...
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... The ECF bit which when set causes an interrupt and the PCA overflow flag CF (in the CCON SFR set when the PCA timer overflows. Rev March, 2001 TS80C51RA2/RD2 TS83C51RB2/RC2/RD2 TS87C51RB2/RC2/RD2 25 ...
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... TS80C51RA2/RD2 TS83C51RB2/RC2/RD2 TS87C51RB2/RC2/RD2 The CCON SFR contains the run control bit for the PCA and the flags for the PCA timer (CF) and each module (Refer to Table 9). Bit CR (CCON.6) must be set by software to run the PCA. The PCA is shut off by clearing this bit. ...
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... The last bit in the register ECOM (CCAPMn.6) when set enables the comparator function. Table 11 shows the CCAPMn settings for the various PCA functions. . Rev March, 2001 CF CR CCF4 CCF3 CCF2 IE.6 ECCFn CCAPMn.0 EC Figure 8. PCA Interrupt System TS80C51RA2/RD2 TS83C51RB2/RC2/RD2 TS87C51RB2/RC2/RD2 CCON CCF1 CCF0 0xD8 To Interrupt priority decoder IE ...
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... TS80C51RA2/RD2 TS83C51RB2/RC2/RD2 TS87C51RB2/RC2/RD2 Table 10. CCAPMn: PCA Modules Compare/Capture Control Registers CCAPM0=0DAH CCAPM1=0DBH CCAPMn Address CCAPM2=0DCH CCAPM3=0DDH CCAPM4=0DEH Reset value Symbol - ECOMn CAPPn CAPNn MATn TOGn PWMn ECCFn a. User software should not write 1s to reserved bits. These bits may be used in future 8051 family products to invoke new features ...
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... Reset value Table 13. CCAPnL: PCA Modules Capture/Compare Registers Low CCAP0L=0EAH CCAP1L=0EBH CCAPnL Address CCAP2L=0ECH CCAP3L=0EDH CCAP4L=0EEH Reset value CH Address 0F9H Reset value CL Address 0E9H Reset value Rev March, 2001 Table 14. CH: PCA Counter High Table 15. CL: PCA Counter Low TS80C51RA2/RD2 TS83C51RB2/RC2/RD2 TS87C51RB2/RC2/RD2 ...
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... TS80C51RA2/RD2 TS83C51RB2/RC2/RD2 TS87C51RB2/RC2/RD2 6.5.1. PCA Capture Mode To use one of the PCA modules in the capture mode either one or both of the CCAPM bits CAPN and CAPP for that module must be set. The external CEX input for the module (on port 1) is sampled for a transition. ...
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... CCAPnH. Of course, the ECOM bit can still be controlled by accessing to CCAPMn register. Rev March, 2001 CCF4 CF CR CCF3 CCAPnL Match 16 bit comparator CH CL PCA counter/timer ECOMn CAPPn CAPNn MATn TOGn PWMn ECCFn CIDL WDTE TS80C51RA2/RD2 TS83C51RB2/RC2/RD2 TS87C51RB2/RC2/RD2 CCON 0xD8 CCF2 CCF1 CCF0 PCA IT RESET * CCAPMn 0xDA to 0xDE CMOD CPS1 CPS0 ECF 0xD9 ...
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... TS80C51RA2/RD2 TS83C51RB2/RC2/RD2 TS87C51RB2/RC2/RD2 6.5.3. High Speed Output Mode In this mode the CEX output (on port 1) associated with the PCA module will toggle each time a match occurs between the PCA counter and the module's capture registers. To activate this mode the TOG, MAT, and ECOM bits in the module's CCAPMn SFR must be set (See Figure 11). ...
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... This watchdog timer won’t generate a reset out on the reset pin. Rev March, 2001 CCAPnH Overflow CCAPnL < 8 bit comparator CL PCA counter/timer CCAPMn 0xDA to 0xDE Figure 12. PCA PWM Mode TS80C51RA2/RD2 TS83C51RB2/RC2/RD2 TS87C51RB2/RC2/RD2 “0” CEXn “1” 33 ...
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... TS80C51RA2/RD2 TS83C51RB2/RC2/RD2 TS87C51RB2/RC2/RD2 6.6. TS80C51Rx2 Serial I/O Port The serial I/O port in the TS80C51Rx2 is compatible with the serial I/O port in the 80C52. It provides both synchronous and asynchronous communication modes. It operates as an Universal Asynchronous Receiver and Transmitter (UART) in three full-duplex modes (Modes 1, 2 and 3). Asynchronous transmission and ...
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... NOTE: The multiprocessor communication and automatic address recognition features cannot be enabled in mode 0 (i.e. setting SM2 bit in SCON register in mode 0 has no effect). Rev March, 2001 Start Data byte bit Figure 14. UART Timings in Mode Start Data byte bit TS80C51RA2/RD2 TS83C51RB2/RC2/RD2 TS87C51RB2/RC2/RD2 D6 D7 Stop bit Ninth Stop bit bit 35 ...
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... TS80C51RA2/RD2 TS83C51RB2/RC2/RD2 TS87C51RB2/RC2/RD2 6.6.3. Given Address Each device has an individual address that is specified in SADDR register; the SADEN register is a mask byte that contains don’t-care bits (defined by zeros) to form the device’s given address. The don’t-care bits provide the flexibility to address one or more slaves at a time. The following example illustrates how a given address is formed. ...
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... SADEN - Slave Address Mask Register (B9h Reset Value = 0000 0000b Not bit addressable SADDR - Slave Address Register (A9h Reset Value = 0000 0000b Not bit addressable Rev March, 2001 TS80C51RA2/RD2 TS83C51RB2/RC2/RD2 TS87C51RB2/RC2/RD2 ...
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... TS80C51RA2/RD2 TS83C51RB2/RC2/RD2 TS87C51RB2/RC2/RD2 SCON - Serial Control Register (98h FE/SM0 SM1 SM2 Bit Bit Number Mnemonic Framing Error bit (SMOD0=1) Clear to reset the error state, not cleared by a valid stop bit Set by hardware when an invalid stop bit is detected. SMOD0 must be set to enable access to the FE bit Serial port Mode bit 0 Refer to SM1 for serial port mode selection ...
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... Reset Value = 00X1 0000b Not bit addressable Power-off flag reset value will be 1 only after a power on (cold reset). A warm reset doesn’t affect the value of this bit. Rev March, 2001 Table 17. PCON Register POF GF1 Description TS80C51RA2/RD2 TS83C51RB2/RC2/RD2 TS87C51RB2/RC2/RD2 GF0 PD IDL 39 ...
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... TS80C51RA2/RD2 TS83C51RB2/RC2/RD2 TS87C51RB2/RC2/RD2 6.7. Interrupt System The TS80C51Rx2 has a total of 7 interrupt vectors: two external interrupts (INT0 and INT1), three timer interrupts (timers 0, 1 and 2), the serial port interrupt and the PCA global interrupt. These interrupts are shown in Figure 16. WARNING: Note that in the first version of RC devices, the PCA interrupt is in the lowest priority. Thus the order in INT0, TF0, INT1, TF1 TI, TF2 or EXF2, PCA ...
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... External interrupt 0 Enable bit 0 EX0 Clear to disable external interrupt 0. Set to enable external interrupt 0. Reset Value = 0000 0000b Bit addressable Rev March, 2001 Table 18. Priority Level Bit Values IP Table 19. IE Register ET1 Description TS80C51RA2/RD2 TS83C51RB2/RC2/RD2 TS87C51RB2/RC2/RD2 Interrupt Level Priority 0 (Lowest (Highest EX1 ET0 EX0 41 ...
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... TS80C51RA2/RD2 TS83C51RB2/RC2/RD2 TS87C51RB2/RC2/RD2 IP - Interrupt Priority Register (B8h PPC PT2 Bit Bit Number Mnemonic Reserved 7 - The value read from this bit is indeterminate. Do not set this bit. PCA interrupt priority bit 6 PPC Refer to PPCH for priority level. Timer 2 overflow interrupt Priority bit ...
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... Description PPC Priority Level 0 Lowest Highest PT2 Priority Level 0 Lowest Highest PS Priority Level 0 Lowest Highest PT1 Priority Level 0 Lowest Highest PX1 Priority Level 0 Lowest Highest PT0 Priority Level 0 Lowest Highest PX0 Priority Level 0 Lowest Highest TS80C51RA2/RD2 TS83C51RB2/RC2/RD2 TS87C51RB2/RC2/RD2 PX1H PT0H PX0H 43 ...
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... TS80C51RA2/RD2 TS83C51RB2/RC2/RD2 TS87C51RB2/RC2/RD2 6.8. Idle mode An instruction that sets PCON.0 causes that to be the last instruction executed before going into the Idle mode. In the Idle mode, the internal clock signal is gated off to the CPU, but not to the interrupt, Timer, and Serial Port functions ...
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... Port 0 can force a "zero" level. A "one" will leave port floating. Rev March, 2001 PSEN PORT0 1 1 Port Data Floating 0 0 Port Data Floating TS80C51RA2/RD2 TS83C51RB2/RC2/RD2 TS87C51RB2/RC2/RD2 PORT1 PORT2 PORT3 Port Data Port Data Port Data Port Data Address Port Data Port Data Port Data Port Data Port Data ...
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... TS80C51RA2/RD2 TS83C51RB2/RC2/RD2 TS87C51RB2/RC2/RD2 6.10. Hardware Watchdog Timer The WDT is intended as a recovery method in situations where the CPU may be subjected to software upset. The WDT consists of a 14-bit counter and the WatchDog Timer ReSeT (WDTRST) SFR. The WDT is by default disabled from exiting reset. To enable the WDT, user must write 01EH and 0E1H in sequence to the WDTRST, SFR location 0A6H ...
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... Idle mode. Rev March, 2001 Table 24. WDTPRG Register Description S1 S0 Selected Time-out machine cycles, 16 MHz machine cycles, 32 MHz machine cycles, 65 MHz machine cycles, 131 MHz machine cycles, 262 MHz machine cycles, 542 MHz machine cycles, 1. MHz machine cycles, 2. MHz TS80C51RA2/RD2 TS83C51RB2/RC2/RD2 TS87C51RB2/RC2/RD2 ...
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... TS80C51RA2/RD2 TS83C51RB2/RC2/RD2 TS87C51RB2/RC2/RD2 TM 6.11. ONCE Mode (ON Chip Emulation) The ONCE mode facilitates testing and debugging of systems using TS80C51Rx2 without removing the circuit from the board. The ONCE mode is invoked by driving certain pins of the TS80C51Rx2; the following sequence must be exercised: Pull ALE low while the device is in reset (RST high) and PSEN is high. ...
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... Reset Value = 00X1 0000b Not bit addressable Rev March, 2001 switch-on. A warm start reset occurs while V CC Table 26. PCON Register POF GF1 Description rises from 0 to its nominal voltage. Can also be set by software. CC TS80C51RA2/RD2 TS83C51RB2/RC2/RD2 TS87C51RB2/RC2/RD2 is still applied GF0 PD IDL rises 49 ...
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... TS80C51RA2/RD2 TS83C51RB2/RC2/RD2 TS87C51RB2/RC2/RD2 6.13. Reduced EMI Mode The ALE signal is used to demultiplex address and data buses on port 0 when used with external program or data memory. Nevertheless, during internal code execution, ALE signal is still generated. In order to reduce EMI, ALE signal can be disabled by setting AO bit. ...
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... MOVC instruction executed from external program memory returns non encrypted data. MOVC instruction executed from external program memory are disabled from fetching U code bytes from internal memory sampled and latched on reset. Same as level 1+ Verify disable. U This security level is only available for 51RDX2 devices. TS80C51RA2/RD2 TS83C51RB2/RC2/RD2 TS87C51RB2/RC2/RD2 51 ...
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... TS80C51RA2/RD2 TS83C51RB2/RC2/RD2 TS87C51RB2/RC2/RD2 8. TS87C51RB2/RC2/RD2 EPROM 8.1. EPROM Structure The TS87C51RB2/RC2/RD2 EPROM is divided in two different arrays: the code array 16/32/64 Kbytes. the encryption array bytes. In addition a third non programmable array is implemented: the signature array bytes. 8.2. EPROM Lock System The program Lock system, when programmed, protects the on-chip program against software piracy. ...
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... Address 0-3Fh Read Signature Bytes 1 Program Lock bit 1 1 Program Lock bit 2 1 Program Lock bit 3 1 Rev March, 2001 Table 30. EPROM Set-Up Modes ALE/ PSEN EA/VPP P2.6 PROG 0 12.75V 12.75V 12.75V 1 0 12.75V 1 0 12.75V 1 TS80C51RA2/RD2 TS83C51RB2/RC2/RD2 TS87C51RB2/RC2/RD2 P2.7 P3.3 P3.6 P3 ...
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... TS80C51RA2/RD2 TS83C51RB2/RC2/RD2 TS87C51RB2/RC2/RD2 PROGRAM SIGNALS* CONTROL SIGNALS MHz * See Table 31. for proper value on these inputs 8.3.3. Programming Algorithm The Improved Quick Pulse algorithm is based on the Quick Pulse algorithm and decreases the number of pulses applied during byte programming from program the TS87C51RB2/RC2/RD2 the following sequence must be exercised: Step 1: Activate the combination of control signals ...
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... If an application subjects the device to this type of exposure suggested that an opaque label be placed over the window. Rev March, 2001 Read/Verify Cycle Data In 100 s TS80C51RA2/RD2 TS83C51RB2/RC2/RD2 TS87C51RB2/RC2/RD2 Data Out 2 rating for 30 minutes distance 55 ...
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... TS80C51RA2/RD2 TS83C51RB2/RC2/RD2 TS87C51RB2/RC2/RD2 9. Signature Bytes The has four signature bytes in location 30h, 31h, 60h and 61h. To read these bytes TS83/87C51RB2/RC2/RD2 follow the procedure for EPROM verify but activate the control lines provided in Table 31. for Read Signature Bytes. Table 31. shows the content of the signature byte for the TS87C51RB2/RC2/RD2. ...
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... Using an internal test ROM, the following code is executed: Label: SJMP Label (80 FE) Ports are disconnected, Port 0 is tied to FFh Vcc, RST = Vss, XTAL2 is not connected and XTAL1 is driven by the clock. This is much more representative of the real operating Icc. Rev March, 2001 TS83C51RB2/RC2/RD2 TS87C51RB2/RC2/RD2 ( - - 150 TS80C51RA2/RD2 57 ...
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... TS80C51RA2/RD2 TS83C51RB2/RC2/RD2 TS87C51RB2/RC2/RD2 10.3. DC Parameters for Standard Voltage + - + Table 32. DC Parameters in Standard Voltage Symbol Parameter V Input Low Voltage IL V Input High Voltage except XTAL1, RST IH V Input High Voltage, XTAL1, RST IH1 V Output Low Voltage, ports (6) Output Low Voltage, port 0 OL1 ...
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... V to 5 MHz 2 5 MHz. CC Min Typ -0.5 0 0 (6) ( (5) 90 (5) 20 (5) 10 TS80C51RA2/RD2 TS83C51RB2/RC2/RD2 TS87C51RB2/RC2/RD2 Max Unit Test Conditions 3 + 0.6 Freq (MHz @12MHz 10.2 @16MHz 12.6 0.25+0.3Freq (MHz @12MHz 3.9 @16MHz 5.1 Max Unit Test Conditions ...
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... TS80C51RA2/RD2 TS83C51RB2/RC2/RD2 TS87C51RB2/RC2/RD2 Symbol Parameter I Power Supply Current Maximum values (7) mode: idle NOTES 1. I under reset is measured with all output pins disconnected; XTAL1 driven with 0.5V; XTAL2 N.C RST = Port Idle I is measured with all output pins disconnected; XTAL1 driven with T CC N.C ...
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... XTAL2 XTAL1 V SS Test Condition, Power-Down Mode CC V -0.5V CC 0.7V CC 0.2V -0.1 0.45V CLCH CHCL 5ns. CLCH CHCL Tests in Active and Idle Modes CC TS80C51RA2/RD2 TS83C51RB2/RC2/RD2 TS87C51RB2/RC2/RD2 All other pins are disconnected. All other pins are disconnected. All other pins are disconnected. 61 ...
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... TS80C51RA2/RD2 TS83C51RB2/RC2/RD2 TS87C51RB2/RC2/RD2 10.5. AC Parameters 10.5.1. Explanation of the AC Symbols Each timing symbol has 5 characters. The first character is always a “T” (stands for time). The other characters, depending on their positions, stand for the name of a signal or the logical status of that signal. The following is a list of all the characters and what they stand for ...
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... Rev March, 2001 Table 36. Symbol Description Parameter Table 37. AC Parameters for Fix Clock - mode standard mode 30 MHz 40 MHz 60 MHz equiv. 40 MHz equiv. Min Max Min Max Min TS80C51RA2/RD2 TS83C51RB2/RC2/RD2 TS87C51RB2/RC2/RD2 -L -L Units X2 mode standard mode 20 MHz 30 MHz Max Min Max 122 ...
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... TS80C51RA2/RD2 TS83C51RB2/RC2/RD2 TS87C51RB2/RC2/RD2 Table 38. AC Parameters for a Variable Clock: derating formula Symbol Type Standard Clock T Min LHLL T Min AVLL T Min LLAX T Max LLIV T Min LLPL T Min PLPH T Max PLIV T Min x PXIX T Max PXIZ T Max AVIV T Max x PLAZ 10.5.3. External Program Memory Read Cycle ...
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... LLDV T Address to Valid Data In AVDV T ALE LLWL T Address AVWL T Data Valid to WR Transition QVWX T Data set- High QVWH T Data Hold After WR WHQX T RD Low to Address Float RLAZ High to ALE high WHLH Rev March, 2001 TS83C51RB2/RC2/RD2 TS87C51RB2/RC2/RD2 Table 39. Symbol Description Parameter TS80C51RA2/RD2 65 ...
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... TS80C51RA2/RD2 TS83C51RB2/RC2/RD2 TS87C51RB2/RC2/RD2 Table 40. AC Parameters for a Fix Clock Speed -M 40 MHz Symbol Min Max T 130 RLRH T 130 WLWH T 100 RLDV T 0 RHDX T 30 RHDZ T 160 LLDV T 165 AVDV T 50 100 LLWL T 75 AVWL T 10 QVWX T 160 QVWH T 15 WHQX T 0 RLAZ ...
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... External Data Memory Write Cycle ALE PSEN WR PORT 0 ADDRESS PORT 2 OR SFR-P2 Figure 26. External Data Memory Write Cycle Rev March, 2001 TS83C51RB2/RC2/RD2 TS87C51RB2/RC2/RD2 X2 Clock - LLWL T QVWX T T LLAX A0-A7 T AVWL ADDRESS A8-A15 OR SFR P2 TS80C51RA2/RD2 -L Units WHLH T WLWH T WHQX QVWH DATA OUT 67 ...
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... TS80C51RA2/RD2 TS83C51RB2/RC2/RD2 TS87C51RB2/RC2/RD2 10.5.6. External Data Memory Read Cycle ALE PSEN RD PORT 0 ADDRESS PORT 2 OR SFR-P2 Figure 27. External Data Memory Read Cycle 10.5.7. Serial Port Timing - Shift Register Mode Symbol T XLXL T QVHX T XHQX T XHDX T XHDV Table 43. AC Parameters for a Fix Clock ...
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... ALE CLOCK T QVXH OUTPUT DATA T WRITE to SBUF XHDV INPUT DATA CLEAR RI Figure 28. Shift Register Timing Waveforms Rev March, 2001 X2 Clock - 133 133 XLXL T XHQX XHDX VALID VALID VALID VALID TS80C51RA2/RD2 TS83C51RB2/RC2/RD2 TS87C51RB2/RC2/RD2 -L Units 133 SET TI VALID VALID VALID VALID SET RI 69 ...
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... TS80C51RA2/RD2 TS83C51RB2/RC2/RD2 TS87C51RB2/RC2/RD2 10.5.9. EPROM Programming and Verification Characteristics 0V Table 45. EPROM Programming Parameters Symbol Parameter V Programming Supply Voltage PP I Programming Supply Current PP 1/T Oscillator Frquency CLCL T Address Setup to PROG Low AVGL T PROG Adress Hold after GHAX T Data Setup to PROG Low DVGL ...
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... CC -0 CHCL CLCX T CLCL 0.2V +0.9 CC 0.2V -0 0.5 for a logic “1” and 0.45V for a logic “0”. Timing measurement CC max for a logic “0”. IL FLOAT -0 LOAD LOAD V +0.1 V LOAD Figure 32. Float Waveforms TS80C51RA2/RD2 TS83C51RB2/RC2/RD2 TS87C51RB2/RC2/RD2 Max Units CHCX T CLCH +0 ...
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... TS80C51RA2/RD2 TS83C51RB2/RC2/RD2 TS87C51RB2/RC2/RD2 For timing purposes a port pin is no longer floating when a 100 mV change from load voltage occurs and begins to float when a 100 mV change from the loaded V 10.5.15. Clock Waveforms Valid in normal clock mode mode XTAL2 signal must be changed to XTAL2 divided by two. ...
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... L: PLCC68 (RD devices only)* M: VQFP64, square package, 1.4mm (RD devices only)* N: JLCC68 (RD devices only)* Temperature Range C: Commercial Industrial - Table 47. Maximum Clock Frequency - TS80C51RA2/RD2 TS83C51RB2/RC2/RD2 TS87C51RB2/RC2/RD2 R B Conditioning R: Tape & Reel D: Dry Pack B: Tape & Reel and Dry Pack -L Unit 30 MHz 30 20 MHz 40 73 ...
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... TS80C51RA2/RD2 TS83C51RB2/RC2/RD2 TS87C51RB2/RC2/RD2 TS80C51RA2/RD2 ROMless -MCA X -MCB X -MCE X -MCL RD2 only -MCM RD2 only -VCA X -VCB X -VCE X -VCL RD2 only -VCM RD2 only -LCA X -LCB X -LCE X -LCL RD2 only -LCM RD2 only -MIA X -MIB X -MIE X -MIL RD2 only -MIM RD2 only ...