TS80C51RA2-VCB Atmel, TS80C51RA2-VCB Datasheet - Page 27

• Manufacturer Part Number: TS80C51RA2-VCB
• Description: IC MCU 8BIT 256BYTE 40MHZ 44PLCC
• Manufacturer: Atmel
• Series: 80Cr

Specifications of TS80C51RA2-VCB

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 40/30MHz
• Connectivity: UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Type: ROMless
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 44-PLCC
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

PCA Modules: each one of the five compare/capture modules has six possible functions. It can perform:
In addition, module 4 can be used as a Watchdog Timer.
Each module in the PCA has a special function register associated with it. These registers are: CCAPM0 for
module 0, CCAPM1 for module 1, etc. (See Table 10). The registers contain the bits that control the mode
that each module will operate in.
Table 11 shows the CCAPMn settings for the various PCA functions.
.
Rev. C - 06 March, 2001
• 16-bit Capture, positive-edge triggered,
• 16-bit Capture, negative-edge triggered,
• 16-bit Capture, both positive and negative-edge triggered,
• 16-bit Software Timer,
• 16-bit High Speed Output,
• 8-bit Pulse Width Modulator.
The ECCF bit (CCAPMn.0 where n=0, 1, 2, 3, or 4 depending on the module) enables the CCF flag in the
CCON SFR to generate an interrupt when a match or compare occurs in the associated module.
PWM (CCAPMn.1) enables the pulse width modulation mode.
The TOG bit (CCAPMn.2) when set causes the CEX output associated with the module to toggle when there
is a match between the PCA counter and the module's capture/compare register.
The match bit MAT (CCAPMn.3) when set will cause the CCFn bit in the CCON register to be set when there
is a match between the PCA counter and the module's capture/compare register.
The next two bits CAPN (CCAPMn.4) and CAPP (CCAPMn.5) determine the edge that a capture input will
be active on. The CAPN bit enables the negative edge, and the CAPP bit enables the positive edge. If both
bits are set both edges will be enabled and a capture will occur for either transition.
The last bit in the register ECOM (CCAPMn.6) when set enables the comparator function.
PCA Timer/Counter
Module 0
Module 1
Module 2
Module 3
Module 4
CMOD.0
ECF
CF
Figure 8. PCA Interrupt System
ECCFn CCAPMn.0
CR
CCF4 CCF3
IE.6
EC
CCF2
TS83C51RB2/RC2/RD2
TS87C51RB2/RC2/RD2
IE.7
EA
CCF1
TS80C51RA2/RD2
CCF0
priority decoder
CCON
0xD8
To Interrupt
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