TS80C51RA2-VCB Atmel, TS80C51RA2-VCB Datasheet - Page 35

• Manufacturer Part Number: TS80C51RA2-VCB
• Description: IC MCU 8BIT 256BYTE 40MHZ 44PLCC
• Manufacturer: Atmel
• Series: 80Cr

Specifications of TS80C51RA2-VCB

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 40/30MHz
• Connectivity: UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Type: ROMless
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 44-PLCC
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Software may examine FE bit after each reception to check for data errors. Once set, only software or a reset can
clear FE bit. Subsequently received frames with valid stop bits cannot clear FE bit. When FE feature is enabled,
RI rises on stop bit instead of the last data bit (See Figure 14. and Figure 15.).
6.6.2. Automatic Address Recognition
The automatic address recognition feature is enabled when the multiprocessor communication feature is enabled
(SM2 bit in SCON register is set).
Implemented in hardware, automatic address recognition enhances the multiprocessor communication feature by
allowing the serial port to examine the address of each incoming command frame. Only when the serial port
recognizes its own address, the receiver sets RI bit in SCON register to generate an interrupt. This ensures that
the CPU is not interrupted by command frames addressed to other devices.
If desired, you may enable the automatic address recognition feature in mode 1. In this configuration, the stop bit
takes the place of the ninth data bit. Bit RI is set only when the received command frame address matches the
device’s address and is terminated by a valid stop bit.
To support automatic address recognition, a device is identified by a given address and a broadcast address.
NOTE: The multiprocessor communication and automatic address recognition features cannot be enabled in mode 0 (i.e. setting SM2 bit in SCON
register in mode 0 has no effect).
Rev. C - 06 March, 2001
SMOD0=X
SMOD0=1
SMOD0=0
SMOD0=1
SMOD0=1
RXD
FE
RI
RXD
FE
RI
RI
Figure 15. UART Timings in Modes 2 and 3
Start
bit
Figure 14. UART Timings in Mode 1
Start
bit
D0
D0
D1
D1
D2
D2
D3
Data byte
D3
Data byte
D4
D4
D5
D5
TS83C51RB2/RC2/RD2
TS87C51RB2/RC2/RD2
D6
D6
D7
TS80C51RA2/RD2
D7
Stop
bit
Ninth
D8
bit
Stop
bit
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