DSPIC30F3010T-20I/SO Microchip Technology, DSPIC30F3010T-20I/SO Datasheet
DSPIC30F3010T-20I/SO
Specifications of DSPIC30F3010T-20I/SO
Related parts for DSPIC30F3010T-20I/SO
DSPIC30F3010T-20I/SO Summary of contents
Page 1
... Microchip Technology Inc. dsPIC30F3010/3011 Data Sheet High Performance Digital Signal Controllers Preliminary DS70141B ...
Page 2
... PowerCal, PowerInfo, PowerMate, PowerTool, rfLAB, rfPICDEM, Select Mode, Smart Serial, SmartTel and Total Endurance are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. ...
Page 3
... All DSP instructions single cycle • ± 16-bit single cycle shift © 2005 Microchip Technology Inc. dsPIC30F3010/3011 Peripheral Features: • High current sink/source I/O pins: 25 mA/25 mA • Timer module with programmable prescaler: - Five 16-bit timers/counters ...
Page 4
... Low power consumption Output Motor EEPROM Timer Input Comp/Std Control Bytes 16-bit Cap PWM PWM 1024 1024 1024 1024 1024 1024 4096 Preliminary A/D 10-bit Quad 500 Ksps Enc 6 ch Yes Yes Yes Yes Yes Yes Yes © 2005 Microchip Technology Inc. ...
Page 5
... PDIP EMUD3/AN0/V EMUC3/AN1/V AN2/SS1/CN4/RB2 AN3/INDX/CN5/RB3 AN4/QEA/IC7/CN6/RB4 AN5/QEB/IC8/CN7/RB5 OSC2/CLKO/RC15 EMUD1/SOSCI/T2CK/U1ATX/CN1/RC13 EMUC1/SOSCO/T1CK/U1ARX/CN0/RC14 EMUD2/OC2/IC2/INT2/RD1 44-Pin TQFP PGC/EMUC/U1RX/SDI1/SDA/RF2 U2TX/CN18/RF5 U2RX/CN17/RF4 RF1 RF0 V V PWM3H/RE5 PWM3L/RE4 PWM2H/RE3 PWM2L/RE2 © 2005 Microchip Technology Inc. dsPIC30F3010/3011 MCLR +/CN2/RB0 REF SS -/CN3/RB1 3 38 PWM1L/RE0 REF 4 37 PWM1H/RE1 5 36 PWM2L/RE2 ...
Page 6
... Pin Diagrams (Continued) 44-Pin QFN PGC/EMUC/U1RX/SDI1/SDA/RF2 U2TX/CN18/RF5 U2RX/CN17/RF4 PWM3H/RE5 PWM3L/RE4 PWM2H/RE3 DS70141B-page RF1 5 29 RF0 6 dsPIC30F3011 Preliminary OSC2/CLKO/RC15 OSC1/CLKIN AN8/RB8 AN7/RB7 AN6/OCFA/RB6 AN5/QEB/IC8/CN7/RB5 AN4/QEA/IC7/CN6/RB4 © 2005 Microchip Technology Inc. ...
Page 7
... SOIC EMUD3/AN0/V REF EMUC3/AN1/V REF AN2/SS1/CN4/RB2 AN3/INDX/CN5/RB3 AN4/QEA/IC7/CN6/RB4 AN5/QEB/IC8/CN7/RB5 OSC1/CLKIN OSC2/CLKO/RC15 EMUD1/SOSCI/T2CK/U1ATX/CN1/RC13 EMUC1/SOSCO/T1CK/U1ARX/CN0/RC14 EMUD2/OC2/IC2/INT2/RD1 44-Pin QFN PGC/EMUC/U1RX/SDI1/SDA/RF2 U2TX/CN18/RF5 U2RX/CN17/RF4 CTX1/RF1 CRX1/RF0 PWM3H/RE5 PWM3L/RE4 PWM2H/RE3 © 2005 Microchip Technology Inc. dsPIC30F3010/3011 MCLR +/CN2/RB0 -/CN3/RB1 PWM1L/RE0 3 26 PWM1H/RE1 4 25 PWM2L/RE2 5 24 PWM2H/RE3 ...
Page 8
... When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are using. Customer Notification System Register on our web site at www.microchip.com to receive the most current information on all of our products. DS70141B-page 6 Preliminary © 2005 Microchip Technology Inc. ...
Page 9
... Family Reference Manual (DS70046). For more information on the device instruction set and programming, refer to the dsPIC30F Programmer’s Reference Manual (DS70030). © 2005 Microchip Technology Inc. dsPIC30F3010/3011 This document contains device specific information for the dsPIC30F3010/3011 ...
Page 10
... PORTF Preliminary EMUD3/AN0/V +/CN2/RB0 REF EMUC3/AN1/V -/CN3/RB1 REF AN2/SS1/CN4/RB2 AN3/INDX/CN5/RB3 AN4/QEA/IC7/CN6/RB4 AN5/QEB/IC8/CN7/RB5 AN6/OCFA/RB6 AN7/RB7 AN8/RB8 EMUD1/SOSCI/T2CK/U1ATX/CN1/RC13 EMUC1/SOSCO/T1CK/U1ARX/CN0/RC14 OSC2/CLKO/RC15 EMUC2/OC1/IC1/INT1/RD0 EMUD2/OC2/IC2/INT2/RD1 OC3/RD2 OC4/RD3 PWM1L/RE0 PWM1H/RE1 PWM2L/RE2 PWM2H/RE3 PWM3L/RE4 PWM3H/RE5 FLTA/INT0/RE8 RF0 RF1 PGC/EMUC/U1RX/SDI1/SDA/RF2 PGD/EMUD/U1TX/SDO1/SCL/RF3 U2RX/CN17/RF4 U2TX/CN18/RF5 SCK1/RF6 © 2005 Microchip Technology Inc. ...
Page 11
... OSC1/CLKI Generation Oscillator Start-up Timer POR/BOR Reset MCLR Watchdog Timer Input 10-bit ADC Capture Module SPI Timers QEI © 2005 Microchip Technology Inc. dsPIC30F3010/3011 X Data Bus Data Latch Data Latch Y Data X Data 16 RAM RAM (4 Kbytes) (4 Kbytes) Address Address Latch Latch RAGU ...
Page 12
... PWM 3 Low output. PWM 3 High output. Master Clear (Reset) input or programming voltage input. This pin is an active low Reset to the device. Compare Fault A input (for Compare channels and 4). Compare outputs 1 through 4. Analog = Preliminary Analog input Output Power © 2005 Microchip Technology Inc. ...
Page 13
... CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels I = Input © 2005 Microchip Technology Inc. dsPIC30F3010/3011 Description Oscillator crystal input. ST buffer when configured in RC mode; CMOS otherwise. Oscillator crystal output. Connects to crystal or resonator in Crystal Oscillator mode. Optionally functions as CLKO in RC and EC modes. ...
Page 14
... PWM 3 Low output. PWM 3 High output. Master Clear (Reset) input or programming voltage input. This pin is an active low Reset to the device. Compare Fault A input (for Compare channels and 4). Compare outputs 1 and 2. Analog = Preliminary Analog input Output Power © 2005 Microchip Technology Inc. ...
Page 15
... CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels I = Input © 2005 Microchip Technology Inc. dsPIC30F3010/3011 Description Oscillator crystal input. ST buffer when configured in RC mode; CMOS otherwise. Oscillator crystal output. Connects to crystal or resonator in Crystal Oscillator mode. Optionally functions as CLKO in RC and EC modes. ...
Page 16
... NOTES: DS70141B-page 14 Preliminary © 2005 Microchip Technology Inc. ...
Page 17
... Moreover, only the lower 16 bits of each instruction word can be accessed using this method. © 2005 Microchip Technology Inc. dsPIC30F3010/3011 • Linear indirect access of 32K word pages within program space is also possible using any working register, via table read and write instructions ...
Page 18
... The upper byte of the SR register contains the DSP Adder/Subtractor status bits, the DO Loop Active bit (DA) and the Digit Carry (DC) status bit. 2.2.3 PROGRAM COUNTER The Program Counter is 23 bits wide. Bit 0 is always clear. Therefore, the PC can address instruction words. Preliminary © 2005 Microchip Technology Inc. ...
Page 19
... Registers AD39 DSP AccA Accumulators AccB PC22 TBLPAG Data Table Page Address PSVPAG OAB SAB DA SRH © 2005 Microchip Technology Inc. dsPIC30F3010/3011 D15 D0 W0/WREG W10 W11 W12/DSP Offset W13/DSP Write Back W14/Frame Pointer W15/Stack Pointer SPLIM AD31 AD15 PC0 0 Program Space Visibility Page Address ...
Page 20
... Unsigned divide: Wm/Wn W0; Rem A block diagram of the DSP engine is shown in Figure 2-2. TABLE 2-2: Instruction CLR ED EDAC MAC MOVSAC MPY MPY.N MSC selection Preliminary W0; Rem W1 W1 DSP INSTRUCTION SUMMARY Algebraic Operation – – change – – © 2005 Microchip Technology Inc. ...
Page 21
... FIGURE 2-2: DSP ENGINE BLOCK DIAGRAM 40 Carry/Borrow Out Carry/Borrow In © 2005 Microchip Technology Inc. dsPIC30F3010/3011 40-bit Accumulator A 40-bit Accumulator B Saturate Adder Negate Barrel 16 Shifter 40 Sign-Extend 17-bit Multiplier/Scaler 16 16 To/From W Array Preliminary Round u Logic Zero Backfill DS70141B-page 19 ...
Page 22
... OVBTEN) in the INTCON1 register (refer to Section 5.0) is set. This allows the user to take immediate action, for example, to correct system gain. Preliminary © 2005 Microchip Technology Inc. ...
Page 23
... No saturation operation is performed and the accumulator is allowed to overflow (destroying its sign). If the COVTE bit in the INTCON1 register is set, a catastrophic overflow can initiate a trap exception. © 2005 Microchip Technology Inc. dsPIC30F3010/3011 2.4.2.2 Accumulator ‘Write Back’ The MAC class of instructions (with the exception of MPY, MPY ...
Page 24
... The barrel shifter is 40 bits wide, thereby obtaining a 40-bit result for DSP shift operations and a 16-bit result for MCU shift operations. Data from the X bus is presented to the barrel shifter between bit positions for right shifts, and bit positions for left shifts. Preliminary © 2005 Microchip Technology Inc. ...
Page 25
... TBLPAG<7> to determine user or configura- tion space access. In Table 3-1, Read/Write instruc- tions, bit 23 allows access to the Device ID, the User ID and the configuration bits. Otherwise, bit 23 is always clear. © 2005 Microchip Technology Inc. dsPIC30F3010/3011 FIGURE 3-1: PROGRAM SPACE MEMORY MAP FOR ...
Page 26
... Note: Program Space Visibility cannot be used to access bits <23:16> word in program memory. DS70141B-page 24 Program Space Address <23> <22:16> 0 TBLPAG<7:0> TBLPAG<7:0> 0 PSVPAG<7:0> 23 bits Program Counter Select bits 15 bits EA 8 bits 16 bits 24-bit EA Preliminary <15> <14:1> <0> PC<22:1> 0 Data EA <15:0> Data EA <15:0> Data EA <14:0> 0 Byte Select © 2005 Microchip Technology Inc. ...
Page 27
... Program Memory ‘Phantom’ Byte (Read as ‘0’). © 2005 Microchip Technology Inc. dsPIC30F3010/3011 A set of Table Instructions are provided to move byte or word-sized data to and from program space. 1. TBLRDL: Table Read Low Word: Read the LS Word of the program address ...
Page 28
... Execution prior to exiting the loop due to an interrupt - Execution upon re-entering the loop after an interrupt is serviced • Any other iteration of the REPEAT loop will allow the instruction, accessing data using PSV, to execute in a single cycle. Preliminary 8 0 space addresses. The © 2005 Microchip Technology Inc. ...
Page 29
... The data space memory is split into two blocks, X and Y data space. A key element of this architecture is that Y space is a subset of X space, and is fully contained within X space. In order to provide an apparent linear addressing space, X and Y spaces have contiguous addresses. © 2005 Microchip Technology Inc. dsPIC30F3010/3011 Program Space 0x0000 (1) PSVPAG ...
Page 30
... Optionally Mapped into Program Memory 0xFFFF DS70141B-page 28 LS Byte 16 bits Address MSB LSB 0x0000 SFR Space 0x07FE 0x0800 X Data RAM (X) 0x09FE 0x0A00 Y Data RAM (Y) 0xBFE 0x0C00 0x8000 X Data Unimplemented (X) 0xFFFE Preliminary 3072 bytes Near Data Space © 2005 Microchip Technology Inc. ...
Page 31
... FIGURE 3-7: DATA SPACE FOR MCU AND DSP (MAC CLASS) INSTRUCTIONS EXAMPLE SFR SPACE (Y SPACE) Non-MAC Class Ops (Read/Write) MAC Class Ops (Write) Indirect EA using any W © 2005 Microchip Technology Inc. dsPIC30F3010/3011 SFR SPACE UNUSED Y SPACE UNUSED MAC Class Ops Read Only ...
Page 32
... FIGURE 3-8: MS Byte 15 0001 0x0000 0003 0x0000 0005 0x0000 Preliminary backward compatibility with DATA ALIGNMENT LS Byte Byte 1 Byte 0 0000 Byte 3 Byte 2 0002 Byte 5 Byte 4 0004 © 2005 Microchip Technology Inc. ...
Page 33
... Note push during exception processing will concatenate the SRL register to the MSB of the PC prior to the push. © 2005 Microchip Technology Inc. dsPIC30F3010/3011 There is a Stack Pointer Limit register (SPLIM) associ- ated with the Stack Pointer. SPLIM is uninitialized at Reset the case for the Stack Pointer, SPLIM<0> ...
Page 34
... DS70141B-page 32 Preliminary © 2005 Microchip Technology Inc. ...
Page 35
... Microchip Technology Inc. dsPIC30F3010/3011 Preliminary DS70141B-page 33 ...
Page 36
... NOTES: DS70141B-page 34 Preliminary © 2005 Microchip Technology Inc. ...
Page 37
... Register Indirect Register Indirect Post-modified Register Indirect Pre-modified Register Indirect with Register Offset The sum of Wn and Wb forms the EA. Register Indirect with Literal Offset © 2005 Microchip Technology Inc. dsPIC30F3010/3011 4.1.1 FILE REGISTER INSTRUCTIONS Most file register instructions use a 13-bit address field (f) to directly address data present in the first 8192 bytes of data memory (near data space) ...
Page 38
... The only exception to the usage restrictions is for buffers which have a power-of-2 length. As these buffers satisfy the start and end address criteria, they may operate in a Bi-directional mode, (i.e., address boundary checks will be performed on both the lower and upper address boundaries). Preliminary © 2005 Microchip Technology Inc. ...
Page 39
... MODULO ADDRESSING OPERATION EXAMPLE Byte Address 0x1100 0x1163 Start Addr = 0x1100 End Addr = 0x1163 Length = 0x0032 words © 2005 Microchip Technology Inc. dsPIC30F3010/3011 4.2.2 W ADDRESS REGISTER SELECTION The Modulo and Bit-Reversed Addressing Control register MODCON<15:0> contains enable flags, as well register field to specify the W address registers ...
Page 40
... W register that has been designated as the bit-reversed pointer. Sequential Address Bit Locations Swapped Left-to-Right Around Center of Binary Value Bit-Reversed Address Pivot Point XB = 0x0008 for a 16-word Bit-Reversed Buffer Preliminary N bytes, addressing and bit-reversed should not be enabled © 2005 Microchip Technology Inc. ...
Page 41
... TABLE 4-2: BIT-REVERSED ADDRESS SEQUENCE (16-ENTRY) Normal Address TABLE 4-3: BIT-REVERSED ADDRESS MODIFIER VALUES FOR XBREV REGISTER Buffer Size (Words) 512 256 128 © 2005 Microchip Technology Inc. dsPIC30F3010/3011 Decimal XB<14:0> Bit-Reversed Address Modifier Value Preliminary Bit-Reversed Address A0 Decimal 0x0100 0x0080 ...
Page 42
... NOTES: DS70141B-page 40 Preliminary © 2005 Microchip Technology Inc. ...
Page 43
... IPL bits. IPL<3> is present in the CORCON register, whereas IPL<2:0> are present in the Status Register (SR) in the processor core. © 2005 Microchip Technology Inc. dsPIC30F3010/3011 • INTCON1<15:0>, INTCON2<15:0> Global interrupt control functions are derived from these two registers. INTCON1 contains the control and status flags for the processor exceptions ...
Page 44
... PWM - PWM Period Match 40 48 QEI - QEI Interrupt 41 49 Reserved 42 50 Reserved 43 51 FLTA - PWM Fault Reserved 45-53 53-61 Reserved Lowest Natural Order Priority * Available on dsPIC30F3011 only Preliminary © 2005 Microchip Technology Inc. Interrupt Source 2 C™ Slave Interrupt 2 C Master Interrupt ...
Page 45
... A momentary dip in the power supply to the device has been detected, which may result in malfunction. • Trap Lockout: Occurrence of multiple trap conditions simulta- neously will cause a Reset. © 2005 Microchip Technology Inc. dsPIC30F3010/3011 5.3 Traps Traps can be considered as non-maskable interrupts indicating a software or hardware error, which adhere to a predefined priority as shown in Figure 5-1 ...
Page 46
... Stack Error Trap Vector Address Error Trap Vector Math Error Trap Vector Reserved Vector AIVT Reserved Vector Reserved Vector Interrupt 0 Vector Interrupt 1 Vector Interrupt 52 Vector Interrupt 53 Vector Preliminary © 2005 Microchip Technology Inc. 0x000000 0x000002 0x000004 0x000014 — — — 0x00007E 0x000080 0x000082 0x000084 0x000094 — ...
Page 47
... The RETFIE (Return from Interrupt) instruction will unstack the program counter and Status registers to return the processor to its state prior to the interrupt sequence. © 2005 Microchip Technology Inc. dsPIC30F3010/3011 5.5 Alternate Vector Table In Program Memory, the Interrupt Vector Table (IVT) is followed by the Alternate Interrupt Vector Table (AIVT), as shown in Figure 5-1 ...
Page 48
... DS70141B-page 46 Preliminary © 2005 Microchip Technology Inc. ...
Page 49
... Using NVMADR Addressing Using Table Instruction User/Configuration Space Select © 2005 Microchip Technology Inc. dsPIC30F3010/3011 6.2 Run Time Self-Programming (RTSP) RTSP is accomplished using TBLRD (table read) and TBLWT (table write) instructions. With RTSP, the user may erase program memory, 32 instructions (96 bytes time and can write program memory data, 32 instructions (96 bytes time ...
Page 50
... NVMKEY register. Refer to Section 6.6 "Programming Operations" for further details. Note: The user can also directly write to the NVMADR and NVMADRU registers to specify a program memory address for erasing or programming. Preliminary © 2005 Microchip Technology Inc. ...
Page 51
... MOV #0xAA,W1 MOV W1 NVMKEY , BSET NVMCON,#WR NOP NOP © 2005 Microchip Technology Inc. dsPIC30F3010/3011 4. Write 32 instruction words of data from data RAM “image” into the program Flash write latches. 5. Program 32 instruction words into program Flash. a) Setup NVMCON register for multi-word, program Flash, program and set WREN bit. ...
Page 52
... Write PM high byte into program latch ; Block all interrupts with priority <7 ; for next 5 instructions ; Write the 0x55 key ; ; Write the 0xAA key ; Start the erase sequence ; Insert two NOPs after the erase ; command is asserted Preliminary © 2005 Microchip Technology Inc. ...
Page 53
... Microchip Technology Inc. dsPIC30F3010/3011 Preliminary DS70141B-page 51 ...
Page 54
... NOTES: DS70141B-page 52 Preliminary © 2005 Microchip Technology Inc. ...
Page 55
... EEPROM write/erase operation. Attempting to read the data EEPROM while a programming or erase operation is in progress results in unspecified data. © 2005 Microchip Technology Inc. dsPIC30F3010/3011 Control bit WR initiates write operations, similar to pro- gram Flash writes. This bit cannot be cleared, only set, in software ...
Page 56
... Block all interrupts with priority <7 ; for next 5 instructions ; ; Write the 0x55 key ; ; Write the 0xAA key ; Initiate erase sequence ; Block all interrupts with priority <7 ; for next 5 instructions ; ; Write the 0x55 key ; ; Write the 0xAA key ; Initiate erase sequence Preliminary © 2005 Microchip Technology Inc. ...
Page 57
... NOP ; Write cycle will complete in 2mS. CPU is not stalled for the Data Write Cycle ; User can poll WR bit, use NVMIF or Timer IRQ to determine write complete © 2005 Microchip Technology Inc. dsPIC30F3010/3011 The write will not initiate if the above sequence is not exactly followed (write 0x55 to NVMKEY, write 0xAA to NVMCON, then set WR bit) for each word ...
Page 58
... EEPROM writes, various mechanisms have been built-in. On power-up, the WREN bit is cleared; also, the Power-up Timer prevents EEPROM write. The write initiate sequence and the WREN bit together, help prevent an accidental write during brown-out, power glitch or software malfunction. Preliminary © 2005 Microchip Technology Inc. ...
Page 59
... WR TRIS WR LAT + WR Port Read LAT Read Port © 2005 Microchip Technology Inc. dsPIC30F3010/3011 Any bit and its associated data and control registers that are not valid for a particular device will be disabled. That means the corresponding LATx and TRISx registers and the port pin will read as zeros. ...
Page 60
... Typically this instruction would be a NOP will be OL EXAMPLE 8-1: MOV 0xFF00, W0 MOV W0, TRISBB NOP btss PORTB, #13 Preliminary I/O Cell I/O Pad Input Data PORT WRITE/READ EXAMPLE ; Configure PORTB<15:8> inputs ; and PORTB<7:0> as outputs ; Delay 1 cycle ; Next Instruction © 2005 Microchip Technology Inc. ...
Page 61
... Microchip Technology Inc. dsPIC30F3010/3011 Preliminary DS70141B-page 59 ...
Page 62
... DS70141B-page 60 Preliminary © 2005 Microchip Technology Inc. ...
Page 63
... Legend uninitialized bit; — = unimplemented bit Note 1: Refer to dsPIC30F Family Reference Manual (DS70046) for descriptions of register bit fields. Not all peripherals, and therefore their bit posi- tions, are available on this device. © 2005 Microchip Technology Inc. dsPIC30F3010/3011 Bit 5 Bit 4 Bit 3 Bit 2 ...
Page 64
... NOTES: DS70141B-page 62 Preliminary © 2005 Microchip Technology Inc. ...
Page 65
... Timer operation during CPU Idle and Sleep modes • Interrupt on 16-bit period register match or falling edge of external gate signal © 2005 Microchip Technology Inc. dsPIC30F3010/3011 These operating modes are determined by setting the appropriate bit(s) in the 16-bit SFR, T1CON. Figure 9-1 presents a block diagram of the 16-bit timer module ...
Page 66
... Period register and be reset to 0x0000. When a match between the timer and the Period register occurs, an interrupt can be generated, if the respective Timer Interrupt Enable bit is asserted. Preliminary TSYNC Sync 1 0 TCKPS<1:0> TON 2 Prescaler 1, 8, 64, 256 © 2005 Microchip Technology Inc. ...
Page 67
... XTAL SOSCO pF 100K © 2005 Microchip Technology Inc. dsPIC30F3010/3011 9.5.1 RTC OSCILLATOR OPERATION When the TON = 1, TCS = 1 and TGATE = 0, the timer increments on the rising edge of the 32 kHz LP oscilla- tor output signal the value specified in the Period register, and is then reset to ‘0’. ...
Page 68
... DS70141B-page 66 Preliminary © 2005 Microchip Technology Inc. ...
Page 69
... Interrupt on a 32-bit Period Register Match These operating modes are determined by setting the appropriate bit(s) in the 16-bit T2CON and T3CON SFRs. © 2005 Microchip Technology Inc. dsPIC30F3010/3011 For 32-bit timer/counter operation, Timer2 is the LS Word and Timer3 is the MS Word of the 32-bit timer. ...
Page 70
... Timer Configuration bit T32, T2CON(<3>) must be set to 1 for a 32-bit timer/counter operation. All control bits are respective to the T2CON register. DS70141B-page 68 16 TMR2 Sync LSB PR2 Q D TGATE(T2CON<6> TON 1 X Gate 0 1 Sync Preliminary TCKPS<1:0> 2 Prescaler 1, 8, 64, 256 © 2005 Microchip Technology Inc. ...
Page 71
... T3IF Event Flag 1 TGATE Note: The dsPIC30F3010/3011 devices do not have external pin inputs to TIMER3. In these devices the following modes should not be used: 1. TCS = 1 2. TCS = 0 and TGATE = 1 (gated time accumulation) © 2005 Microchip Technology Inc. dsPIC30F3010/3011 PR2 TMR2 Q D TGATE CK Q TON ...
Page 72
... In this mode, the T3IF interrupt flag is used as the source of the interrupt. The T3IF bit must be cleared in software. Enabling an interrupt is accomplished via the respective Timer Interrupt Enable bit, T3IE (IEC0<7>). Preliminary © 2005 Microchip Technology Inc. ...
Page 73
... Microchip Technology Inc. dsPIC30F3010/3011 Preliminary DS70141B-page 71 ...
Page 74
... NOTES: DS70141B-page 72 Preliminary © 2005 Microchip Technology Inc. ...
Page 75
... The dsPIC30F3010/3011 devices do not have external pin inputs to TIMER4 or TIMER5. In these devices the following modes should not be used: 1. TCS = 1 2. TCS = 0 and TGATE = 1 (gated time accumulation) © 2005 Microchip Technology Inc. dsPIC30F3010/3011 The Timer4/5 module is similar in operation to the Timer 2/3 module. However, there are some differences, which are as follows: • ...
Page 76
... The dsPIC30F3010/3011 devices do not have external pin inputs to TIMER4 or TIMER5. In these devices the following modes should not be used: 1. TCS = 1 2. TCS = 0 and TGATE = 1 (gated time accumulation) DS70141B-page 74 PR4 TMR4 Q D TGATE CK Q TON 1 X Gate Sync Preliminary Sync TCKPS<1:0> 2 Prescaler 1, 8, 64, 256 © 2005 Microchip Technology Inc. ...
Page 77
... Event Flag 1 TGATE Note: The dsPIC30F3010/3011 devices do not have external pin inputs to TIMER4 or TIMER5. In these devices the following modes should not be used: 1. TCS = 1 2. TCS = 0 and TGATE = 1 (gated time accumulation) © 2005 Microchip Technology Inc. dsPIC30F3010/3011 PR5 Comparator x 16 TMR5 Q D TGATE ...
Page 78
... DS70141B-page 76 Preliminary © 2005 Microchip Technology Inc. ...
Page 79
... ICxCON Data Bus Note: Where ‘x’ is shown, reference is made to the registers or bits associated to the respective input capture channels 1 through N. © 2005 Microchip Technology Inc. dsPIC30F3010/3011 The key operational features of the Input Capture module are: • Simple Capture Event mode • Timer2 and Timer3 mode selection • ...
Page 80
... The capture module must be configured for interrupt only on the rising edge (ICM<2:0> = 111) in order for the input capture module to be used while the device is in Sleep mode. The prescale settings of 4:1 or 16:1 are not applicable in this mode. Preliminary © 2005 Microchip Technology Inc. ...
Page 81
... ICSIDL bit must be asserted to a logic ‘0’. If the input capture module is defined as ICM<2:0> = 111 in CPU Idle mode, the input capture pin will serve only as an external interrupt pin. © 2005 Microchip Technology Inc. dsPIC30F3010/3011 12.3 Input Capture Interrupts The input capture channels have the ability to generate an interrupt, based upon the selected number of capture events ...
Page 82
... DS70141B-page 80 Preliminary © 2005 Microchip Technology Inc. ...
Page 83
... TMR3<15:0> TMR2<15:0 Note: Where ‘x’ is shown, reference is made to the registers associated with the respective output compare channels 1 through N. © 2005 Microchip Technology Inc. dsPIC30F3010/3011 The key operational features of the Output Compare module include: • Timer2 and Timer3 Selection mode • Simple Output Compare Match mode • ...
Page 84
... FAULT condition has occurred. This state will be maintained until both of the following events have occurred: • The external FAULT condition has been removed. • The PWM mode has been re-enabled by writing to the appropriate control bits. Preliminary . © 2005 Microchip Technology Inc. ...
Page 85
... CPU Idle mode if the OCSIDL bit (OCxCON<13> logic 0 and the selected time base (Timer2 or Timer3) is enabled and the TSIDL bit of the selected timer is set to logic 0. © 2005 Microchip Technology Inc. dsPIC30F3010/3011 When the selected TMRx is equal to its respective period register, PRx, the following four events occur on the next increment cycle: • ...
Page 86
... DS70141B-page 84 Preliminary © 2005 Microchip Technology Inc. ...
Page 87
... INDX Digital Filter 3 Note 1: In dsPIC30F3010/3011, the UPDN pin is not available. Up/Down logic bit can still be polled by software. © 2005 Microchip Technology Inc. dsPIC30F3010/3011 The operational features of the QEI include: • Three input channels for two phase signals and index pulse • ...
Page 88
... As mentioned in the previous section, the QEI logic generates an UPDN signal, based upon the relation- ship between Phase A and Phase B. In addition to the output pin, the state of this internal UPDN signal is supplied to a SFR bit UPDN (QEICON<11> read only bit. Preliminary © 2005 Microchip Technology Inc. ...
Page 89
... CY To enable the filter output for channels QEA, QEB and INDX, the QEOUT bit must be ‘1’. The filter network for all channels is disabled on POR and BOR. © 2005 Microchip Technology Inc. dsPIC30F3010/3011 14.5 Alternate 16-bit Timer/Counter When the QEI module is not configured for the QEI mode QEIM< ...
Page 90
... The QEIIF bit must be cleared in software. QEIIF is located in the IFS2 status register. Enabling an interrupt is accomplished via the respec- tive Enable bit, QEIIE. The QEIIE bit is located in the IEC2 control register. QEISIDL bit Preliminary © 2005 Microchip Technology Inc. ...
Page 91
... Microchip Technology Inc. dsPIC30F3010/3011 Preliminary DS70141B-page 89 ...
Page 92
... NOTES: DS70141B-page 90 Preliminary © 2005 Microchip Technology Inc. ...
Page 93
... Uninterruptible Power Supply (UPS) The PWM module has the following features: • 6 PWM I/O pins with 3 duty cycle generators • 16-bit resolution © 2005 Microchip Technology Inc. dsPIC30F3010/3011 • ‘On-the-Fly’ PWM frequency changes • Edge and Center-aligned Output modes • ...
Page 94
... Override Logic PWM Generator Channel 2 Dead-Time #2 PWM Generator Channel 1 Dead-Time #1 Special Event Postscaler SEVTDIR PTDIR Preliminary PWM3H PWM3L PWM2H Output Generator and PWM2L Override Logic Driver Block PWM1H Generator and PWM1L Override Logic FLTA Special Event Trigger © 2005 Microchip Technology Inc. ...
Page 95
... The interrupt signals generated by the PWM time base depend on the mode selection bits (PTMOD<1:0>) and the postscaler bits (PTOPS<3:0>) in the PTCON SFR. © 2005 Microchip Technology Inc. dsPIC30F3010/3011 15.1.1 FREE RUNNING MODE In the Free Running mode, the PWM time base counts upwards until the value in the Time Base Period register (PTPER) is matched ...
Page 96
... PWM pin will be active for the entire PWM period if the value in the duty cycle register is greater than the value held in the PTPER register. FIGURE 15-2: EDGE-ALIGNED PWM PTPER PTMR Value 0 Duty Cycle Period Preliminary © 2005 Microchip Technology Inc. be determined using • (PTPER + 1) • PWM CY ...
Page 97
... The duty cycle registers are 16-bits wide. The LS bit of a duty cycle register determines whether the PWM edge occurs in the beginning. Thus, the PWM resolution is effectively doubled. © 2005 Microchip Technology Inc. dsPIC30F3010/3011 15.5.1 DUTY CYCLE REGISTER BUFFERS The three PWM duty cycle registers are double buff- ered to allow glitchless updates of the PWM outputs ...
Page 98
... On a load of the down timer due to a duty cycle comparison edge event. • write to the DTCON1 register. • On any device Reset. Note: The user should not modify the DTCON1 value while the PWM module is operating (PTEN = 1). Unexpected results may occur. Dead Time Preliminary © 2005 Microchip Technology Inc may ...
Page 99
... PTPER register occurs, the PTMR register is cleared, all active PWM I/O pins are driven to the inactive state, the PTEN bit is cleared and an interrupt is generated. © 2005 Microchip Technology Inc. dsPIC30F3010/3011 15.10 PWM Output Override The PWM output override bits allow the user to manually drive the PWM I/O pins to specified logic states, independent of the duty cycle comparison units ...
Page 100
... PWM outputs return to normal operation at the beginning of the following PWM cycle or half-cycle boundary. The Operating mode for the FAULT input pin is selected using the FLTAM control bit in the FLTACON special function register. The FAULT pin can be controlled manually in software. Preliminary © 2005 Microchip Technology Inc. ...
Page 101
... PWM time base. The SEVTDIR control bit has no effect unless the PWM time base is configured for an Up/Down Counting mode. © 2005 Microchip Technology Inc. dsPIC30F3010/3011 15.14.1 SPECIAL EVENT TRIGGER POSTSCALER The PWM special event trigger has a postscaler that allows a 1:1 to 1:16 postscale ratio ...
Page 102
... DS70141B-page 100 Preliminary © 2005 Microchip Technology Inc. ...
Page 103
... Note: Both the transmit buffer (SPI1TXB) and the receive buffer (SPI1RXB) are mapped to the same register address, SPI1BUF. © 2005 Microchip Technology Inc. dsPIC30F3010/3011 In Master mode, the clock is generated by prescaling the system clock. Data is transmitted as soon as a value is written to SPI1BUF. The interrupt is generated at the middle of the transfer of the last bit ...
Page 104
... Edge Control Select Enable Master Clock SDOx SDIy SDIx SDOy LSb Serial Clock SCKx SCKy Preliminary Secondary Primary F Prescaler Prescaler CY 1:1 – 1 16, 64 SPI™ Slave Serial Input Buffer (SPIyBUF) Shift Register (SPIySR) MSb LSb PROCESSOR 2 © 2005 Microchip Technology Inc. ...
Page 105
... Therefore, when the SS1 pin is asserted low again, transmission/reception will begin at the MS bit, even if SS1 has been de-asserted in the middle of a transmit/receive. Note that in dsPIC30F4012, the SS1 pin is not available. © 2005 Microchip Technology Inc. dsPIC30F3010/3011 16.4 SPI Operation During CPU Sleep Mode During Sleep mode, the SPI module is shut-down ...
Page 106
... DS70141B-page 104 Preliminary © 2005 Microchip Technology Inc. ...
Page 107
... Thus, the I C module can operate either as a slave master bus. FIGURE 17-1: PROGRAMMER’S MODEL bit 15 bit 15 © 2005 Microchip Technology Inc. dsPIC30F3010/3011 17.1.1 VARIOUS I The following types • Slave operation with 7-bit address 2 • Slave operation with 10-bit address 2 • ...
Page 108
... Match Detect I2CADD Start and Start, Restart, Collision Detect Acknowledge Generation Clock Stretching I2CTRN LSB Reload Control I2CBRG BRG Down Counter F CY Preliminary Internal Data Bus Read Write Read Write Read Write Read Write Read Write Read © 2005 Microchip Technology Inc. ...
Page 109
... SDA is valid during SCL high (see timing diagram). The interrupt pulse is sent on the falling edge of the ninth clock pulse, regardless of the status of the ACK received from the master. © 2005 Microchip Technology Inc. dsPIC30F3010/3011 17.3.2 SLAVE RECEPTION If the R_W bit received is a ‘0’ during an address match, then Receive mode is initiated ...
Page 110
... This ensures that a write to the SCLREL bit will not violate the minimum high time requirement for SCL. If the STREN bit is ‘0’, a software write to the SCLREL bit will be disregarded and have no effect on the SCLREL bit. Preliminary © 2005 Microchip Technology Inc. ...
Page 111
... When the interrupt is serviced, the source for the interrupt can be checked by reading the contents of the I2CRCV to determine if the address was device specific general call address. © 2005 Microchip Technology Inc. dsPIC30F3010/3011 2 17. Master Support As a Master device, six operations are supported. ...
Page 112
... Idle or continue on Idle. If I2CSIDL = 0, the module will continue operation on assertion of the Idle mode. If I2CSIDL = 1, the module will stop on Idle. Preliminary 2 C master event Interrupt Service 2 C bus is free (i.e., the P bit is set) the 2 C bus © 2005 Microchip Technology Inc. ...
Page 113
... Microchip Technology Inc. dsPIC30F3010/3011 Preliminary DS70141B-page 111 ...
Page 114
... NOTES: DS70141B-page 112 Preliminary © 2005 Microchip Technology Inc. ...
Page 115
... UTXBRK Data UxTX Parity Note dsPIC30F3010 only has UART1. © 2005 Microchip Technology Inc. dsPIC30F3010/3011 18.1 UART Module Overview The key features of the UART module are: • Full-duplex 9-bit data communication • Even, Odd or No Parity options (for 8-bit data) • One or two Stop bits • ...
Page 116
... Receive Buffer Control – Generate Flags – Generate Interrupt – Shift Data Characters 8-9 Load RSR to Buffer Receive Shift Register (UxRSR) 16 Divider 16X Baud Clock from Baud Rate Generator Preliminary Read Read Write UxMODE UxSTA Control Signals UxRXIF © 2005 Microchip Technology Inc. ...
Page 117
... The STSEL bit determines whether one or two stop bits will be used during data transmission. The default (Power-on) setting of the UART is 8 bits, no parity, 1 stop bit (typically represented 1). © 2005 Microchip Technology Inc. dsPIC30F3010/3011 18.3 Transmitting Data 18.3.1 ...
Page 118
... UxRSR needs to transfer the character to the buffer. Once OERR is set, no further data is shifted in UxRSR (until the OERR bit is cleared in software or a Reset occurs). The data held in UxRSR and UxRXREG remains valid. Preliminary © 2005 Microchip Technology Inc. RXB) X ...
Page 119
... FERR bit set. The break character is loaded into the buffer. No further reception can occur until a stop bit is received. Note that RIDLE goes high when the stop bit has not been received yet. © 2005 Microchip Technology Inc. dsPIC30F3010/3011 18.6 Address Detect Mode Setting the ADDEN bit (UxSTA< ...
Page 120
... For the UART, the USIDL bit selects if the module will stop operation when the device enters Idle mode, or whether the module will continue on Idle. If USIDL = 0, the module will continue operation during Idle mode. If USIDL = 1, the module will stop on Idle. Preliminary © 2005 Microchip Technology Inc. ...
Page 121
... Microchip Technology Inc. dsPIC30F3010/3011 Preliminary DS70141B-page 119 ...
Page 122
... NOTES: DS70141B-page 120 Preliminary © 2005 Microchip Technology Inc. ...
Page 123
... SS REF A/D converter has a unique feature of being able to operate while the device is in Sleep mode. © 2005 Microchip Technology Inc. dsPIC30F3010/3011 The A/D module has six 16-bit registers: • A/D Control register1 (ADCON1) • A/D Control register2 (ADCON2) • A/D Control register3 (ADCON3) • ...
Page 124
... AN1 * = Not available on dsPIC30F3010. DS70141B-page 122 CH1 ADC S/H - 10-bit Result + CH2 S/H - 16-word, 10-bit + CH3 S/H CH1,CH2, - CH3,CH0 Sample/Sequence sample input switches + CH0 S/H - Preliminary Conversion Logic Dual Port Buffer Control Input Mux Control © 2005 Microchip Technology Inc. ...
Page 125
... The channels are then converted sequentially. Obvi- ously, if there is only 1 channel selected, the SIMSAM bit is not applicable. © 2005 Microchip Technology Inc. dsPIC30F3010/3011 The CHPS bits selects how many channels are sam- pled. This can vary from channels. If CHPS selects 1 channel, the CH0 channel will be sampled at the sample clock and converted ...
Page 126
... Preliminary . The source of the A/D CONVERSION CLOCK = T * (0.5*(ADCS<5:0> +1 ADCS<5:0> – time AD = 5V). Refer to the Section 23.0 DD under AD A/D CONVERSION CLOCK CALCULATION = 154 nsec nsec (30 MIPS – 154 nsec = 2 • – nsec = 8. (ADCS<5:0> nsec = ( 165 nsec © 2005 Microchip Technology Inc. ...
Page 127
... DAC) HOLD Note: C value depends on device package and is not tested. Effect of C PIN © 2005 Microchip Technology Inc. dsPIC30F3010/3011 The user must allow at least 1 T time between conversions to allow each SAMP sample to be acquired. This sample time may be ...
Page 128
... Each of the output formats translates to a 16-bit result on the data bus. Write data will always be in right justified (integer) format. d09 d08 d07 d06 d05 d04 d03 d02 d01 d00 d09 d08 d07 d06 d05 d04 d03 d02 d01 d00 Preliminary © 2005 Microchip Technology Inc. ...
Page 129
... Analog levels on any pin that is defined as a digital input (including the ANx pins) may cause the input buffer to consume current that exceeds the device specifications. © 2005 Microchip Technology Inc. dsPIC30F3010/3011 19.13 Connection Considerations The analog inputs have diodes to V protection ...
Page 130
... DS70141B-page 128 Preliminary © 2005 Microchip Technology Inc. ...
Page 131
... In the Idle mode, the clock sources are still active, but the CPU is shut-off. The RC oscillator option saves system cost, while the LP crystal option saves power. © 2005 Microchip Technology Inc. dsPIC30F3010/3011 20.1 Oscillator System Overview The dsPIC30F oscillator system has the following modules and features: • ...
Page 132
... Note 1: dsPIC30F maximum operating frequency of 120 MHz must be met oscillator can be conveniently shared as system clock, as well as real-time clock for Timer1. 3: Requires external R and C. Frequency operation MHz. DS70141B-page 130 Description (1) . (2) . (1) . (1) . (3) /4 output . OSC (3) . Preliminary © 2005 Microchip Technology Inc. (1) . (1) . (1) . ...
Page 133
... FIGURE 20-1: OSCILLATOR SYSTEM BLOCK DIAGRAM OSC1 Primary Oscillator OSC2 TUN<3:0> 4 Internal Fast RC Oscillator (FRC) POR Done SOSCO 32 kHz LP Oscillator SOSCI © 2005 Microchip Technology Inc. dsPIC30F3010/3011 F PLL PLL x4, x8, x16 PLL Lock Primary Osc Primary Oscillator Stability Detector Oscillator Start-up Timer ...
Page 134
... OSC2 Function OSC2 0 1 OSC2 1 0 OSC2 1 1 OSC2 0 1 OSC2 1 0 OSC2 1 1 OSC2 0 1 OSC2 1 0 OSC2 OSC2 0 0 OSC2 1 0 CLKOUT 1 1 CLKOUT OSC2 0 0 (Note (Note (Note © 2005 Microchip Technology Inc. ...
Page 135
... Table 20-4. If OSCCON<14:12> are set to ‘111’ and FPR<4:0> are set to ‘00101’, ‘00110’ or ‘00111’, then a PLL multiplier (respectively) is applied © 2005 Microchip Technology Inc. dsPIC30F3010/3011 . Note: When a 16x PLL is used, the FRC fre- quency must not be tuned to a frequency greater than 7 ...
Page 136
... Byte Write “0x78” to OSCCON high Byte Write “0x9A” to OSCCON high Byte Write is allowed for one instruction cycle . Write the desired value or use bit manipulation instruction. Preliminary © 2005 Microchip Technology Inc. ...
Page 137
... POR timer and place the device in the Reset state. The POR also selects the device clock source identified by the oscillator configuration fuses. © 2005 Microchip Technology Inc. dsPIC30F3010/3011 Different registers are affected in different ways by various Reset conditions. Most registers are not affected by a WDT wake-up, since this is viewed as the resumption of normal operation ...
Page 138
... INTERNAL POR OST TIME-OUT PWRT TIME-OUT INTERNAL Reset FIGURE 20-5: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED MCLR INTERNAL POR OST TIME-OUT PWRT TIME-OUT INTERNAL Reset DS70141B-page 136 T OST T PWRT T OST T PWRT T OST T PWRT Preliminary ) DD ): CASE CASE 2 DD © 2005 Microchip Technology Inc. ...
Page 139
... Note: The BOR voltage trip points indicated here are nominal values provided for design guidance only. © 2005 Microchip Technology Inc. dsPIC30F3010/3011 A BOR will generate a Reset pulse which will reset the device. The BOR will select the clock source, based on the device configuration bit values (FOS<1:0> and FPR< ...
Page 140
... When the wake-up is due to an enabled interrupt, the PC is loaded with the corresponding interrupt vector. DS70141B-page 138 TRAPR IOPUWR EXTR SWR WDTO IDLE SLEEP POR BOR ( TRAPR IOPUWR EXTR SWR WDTO IDLE SLEEP POR BOR ( Preliminary © 2005 Microchip Technology Inc. ...
Page 141
... PWRSAV. These are: Sleep and Idle. The format of the PWRSAV instruction is as follows: PWRSAV <parameter>, where ‘parameter’ defines Idle or Sleep mode. © 2005 Microchip Technology Inc. dsPIC30F3010/3011 20.5.1 SLEEP MODE In Sleep mode, the clock to the CPU and peripherals is shutdown ...
Page 142
... For additional information, please refer to the programming specifications of the device. Note: If the code protection configuration fuse bits (FGS<GCP> and FGS<GWRP>) have been programmed, an erase of the entire code-protected device is only possible at voltages V Preliminary 4.5V. DD © 2005 Microchip Technology Inc. ...
Page 143
... MPLAB IDE. These pin pairs are named EMUD/EMUC, EMUD1/ EMUC1, EMUD2/EMUC2 and EMUD3/EMUC3. © 2005 Microchip Technology Inc. dsPIC30F3010/3011 In each case, the selected EMUD pin is the Emulation/ Debug Data line, and the EMUC pin is the Emulation/ Debug Clock line ...
Page 144
... DS70141B-page 142 Preliminary © 2005 Microchip Technology Inc. ...
Page 145
... The File register specified by the value ‘f’ • The destination, which could either be the File register ‘f’ or the W0 register, which is denoted as ‘WREG’ © 2005 Microchip Technology Inc. dsPIC30F3010/3011 Most bit oriented instructions (including simple rotate/ shift instructions) have two operands: • ...
Page 146
... Programmer’s Reference Manual (DS70030). Description {W13, [W13]+=2} {0x0000...0x1FFF} {0,1} {0...15} {0...31} {0...255} {0...255} for Byte mode, {0:1023} for Word mode {0...16384} {0...65535} {0...8388608}; LSB must be 0 {-512...511} {-32768...32767} {-16...16} Preliminary © 2005 Microchip Technology Inc. {0...15} ...
Page 147
... Y data space Pre-fetch Address register for DSP instructions Wy {[W10]+=6, [W10]+=4, [W10]+=2, [W10], [W10]-=6, [W10]-=4, [W10]-=2, [W11]+=6, [W11]+=4, [W11]+=2, [W11], [W11]-=6, [W11]-=4, [W11]-=2, [W11+W12], none} Y data space Pre-fetch Destination register for DSP instructions Wyd © 2005 Microchip Technology Inc. dsPIC30F3010/3011 Description {W0..W15} { Wd, [Wd], [Wd++], [Wd--], [++Wd], [--Wd] } {W0..W15} {W0..W15} {W0 ...
Page 148
... Branch if Overflow Branch if accumulator A saturated Branch if accumulator B saturated Branch Unconditionally Branch if Zero Computed Branch Bit Set f Bit Set Ws Write C bit to Ws<Wb> Write Z bit to Ws<Wb> Bit Toggle f Bit Toggle Ws Preliminary © 2005 Microchip Technology Inc Status Flags cycle words Affected OA,OB,SA, C,DC,N,OV,Z ...
Page 149
... DEC Ws,Wd 28 DEC2 DEC2 f DEC2 f,WREG DEC2 Ws,Wd © 2005 Microchip Technology Inc. dsPIC30F3010/3011 Description Bit Test f, Skip if Clear Bit Test Ws, Skip if Clear Bit Test f, Skip if Set Bit Test Ws, Skip if Set Bit Test f Bit Test Bit Test Bit Test Ws<Wb> Bit Test Ws< ...
Page 150
... Move Move WREG to f Move Double from W(ns):W( Move Double from Ws to W(nd ):W(nd) +1 Pre-fetch and store accumulator Multiply Accumulator Square Wm to Accumulator -(Multiply Wm by Wn) to Accumulator Preliminary © 2005 Microchip Technology Inc Status Flags cycle words Affected None 1 18 N,Z,C, OV ...
Page 151
... SE Ws,Wnd 70 SETM SETM f SETM WREG SETM Ws © 2005 Microchip Technology Inc. dsPIC30F3010/3011 Description Multiply and Subtract from Accumulator {Wnd+1, Wnd} = signed(Wb) * signed(Ws) {Wnd+1, Wnd} = signed(Wb) * unsigned(Ws) {Wnd+1, Wnd} = unsigned(Wb) * signed(Ws) {Wnd+1, Wnd} = unsigned(Wb) * unsigned(Ws) {Wnd+1, Wnd} = signed(Wb) * unsigned(lit5) {Wnd+1, Wnd} = unsigned(Wb) * ...
Page 152
... Wn = byte swap Wn Read Prog<23:16> to Wd<7:0> Read Prog<15:0> Write Ws<7:0> to Prog<23:16> Write Ws to Prog<15:0> Unlink frame pointer .XOR. WREG WREG = f .XOR. WREG Wd = lit10 .XOR .XOR .XOR. lit5 Wnd = Zero-Extend Ws Preliminary © 2005 Microchip Technology Inc Status Flags cycle words Affected OA,OB,OAB, SA,SB,SAB 1 ...
Page 153
... RFID products - CAN ® - PowerSmart Battery Management - Analog © 2005 Microchip Technology Inc. dsPIC30F3010/3011 22.1 MPLAB Integrated Development Environment Software The MPLAB IDE software brings an ease of software development previously unseen in the 8/16-bit micro- controller market. The MPLAB IDE is a Windows based application that contains: • ...
Page 154
... MPLAB C30 C Compiler and MPLAB ASM30 assembler. The simulator runs in either a Command Line mode for automated tasks, or from MPLAB IDE. This high-speed simulator is designed to debug, analyze and optimize time intensive DSP routines. Preliminary © 2005 Microchip Technology Inc. economical software ...
Page 155
... The PC platform and Microsoft Windows 32-bit operating system were chosen to best make these features available in a simple, unified application. © 2005 Microchip Technology Inc. dsPIC30F3010/3011 22.11 MPLAB ICD 2 In-Circuit Debugger Microchip’s In-Circuit Debugger, MPLAB ICD powerful, ...
Page 156
... H-Bridge motor driver, LIN transceiver and EEPROM. Also included are: header for expansion, eight LEDs, four potentiometers, three push buttons and a proto- typing area. Included with the kit is a PIC16F627A and a PIC18F1320. Tutorial firmware is included along with the User’s Guide. Preliminary © 2005 Microchip Technology Inc. ...
Page 157
... PIC Microcontrollers” Handbook and a USB interface cable. Supports all current 8/14-pin Flash PIC microcontrollers, as well as many future planned devices. © 2005 Microchip Technology Inc. dsPIC30F3010/3011 22.24 PICDEM USB PIC16C7X5 Demonstration Board The PICDEM USB Demonstration Board shows off the capabilities of the PIC16C745 and PIC16C765 USB microcontrollers ...
Page 158
... NOTES: DS70141B-page 156 Preliminary © 2005 Microchip Technology Inc. ...
Page 159
... Range Temp Range DD 4.5-5.5V -40°C to 85°C 4.5-5.5V -40°C to 125°C 3.0-3.6V -40°C to 85°C 3.0-3.6V -40°C to 125°C 2.5-3.0V -40°C to 85°C © 2005 Microchip Technology Inc. dsPIC30F3010/3011 (except V and MCLR) (Note 1) ..................................... -0. ....................................................................................................... 0V to +13.25V ) ..........................................................................................................± > ................................................................................................... ± Max MIPS dsPIC30F301x-30I ...
Page 160
... INT Typ Max Unit Notes 42 °C °C °C °C °C/W 1 -40°C T +85°C for Industrial A -40°C T +125°C for Extended A Units Conditions V Industrial temperature V Extended temperature V V V/ms 0-5V in 0.1 sec 0- © 2005 Microchip Technology Inc. ...
Page 161
... All I/O pins are configured as inputs and pulled to V MCLR = V , WDT, FSCM, LVD and BOR are disabled. CPU, SRAM, program memory and data memory DD are operational. No peripheral modules are operating. © 2005 Microchip Technology Inc. dsPIC30F3010/3011 ) DD Standard Operating Conditions: 2.5V to 5.5V ...
Page 162
... OSC1 DD Preliminary +85°C for Industrial +125°C for Extended 20 MIPS EC mode, 8X PLL 16 MIPS EC mode, 16X PLL 30 MIPS EC mode, 16X PLL FRC (~ 2 MIPS) LPRC (~ 512 kHz © 2005 Microchip Technology Inc. ...
Page 163
... Data in “Typical” column is at 5V, 25°C unless otherwise stated. Parameters are for design guidance only and are not tested. 2: Base I current is measured with core off, clock on and all modules turned off. IDLE © 2005 Microchip Technology Inc. dsPIC30F3010/3011 ) IDLE Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) Operating temperature -40° ...
Page 164
... V mA 85°C mA 125°C Preliminary +85°C for Industrial +125°C for Extended 20 MIPS EC mode, 8X PLL 16 MIPS EC mode, 16X PLL 30 MIPS EC mode, 16X PLL FRC (~ 2 MIPS) LPRC (~ 512 kHz) © 2005 Microchip Technology Inc. ...
Page 165
... LVD, BOR, WDT, etc. are all switched off. 3: The current is the additional current consumed when the module is enabled. This current should be added to the base I current. PD © 2005 Microchip Technology Inc. dsPIC30F3010/3011 Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) Operating temperature -40° -40° ...
Page 166
... Preliminary -40°C T +85°C for Industrial A -40°C T +125°C for Extended A Units Conditions SMbus disabled V SMbus enabled SMbus disabled V SMbus enabled 5V PIN 3V PIN PIN DD Pin at hi-impedance PIN DD Pin at hi-impedance PIN XT PIN DD and LP Osc mode © 2005 Microchip Technology Inc. ...
Page 167
... These parameters are characterized but not tested in manufacturing. FIGURE 23-1: BROWN-OUT RESET CHARACTERISTICS V DD BO10 (Device in Brown-out Reset) RESET (due to BOR) © 2005 Microchip Technology Inc. dsPIC30F3010/3011 Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) Operating temperature -40°C -40°C (1) Min Typ ...
Page 168
... V 4.46 V 4.78 V — +85°C for Industrial A T +125°C for Extended A Conditions - +85° Using EECON to read/write V = Minimum operating MIN voltage ms are violated Row Erase - +85° Minimum operating MIN voltage are violated ms Row Erase Bulk Erase © 2005 Microchip Technology Inc. ...
Page 169
... FIGURE 23-2: LOAD CONDITIONS FOR DEVICE TIMING SPECIFICATIONS Load Condition 1 - for all pins except OSC2 Pin FIGURE 23-3: EXTERNAL CLOCK TIMING Q4 OSC1 CLKOUT © 2005 Microchip Technology Inc. dsPIC30F3010/3011 Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) Operating temperature -40°C T -40°C T Operating voltage V range as described in DC Spec Section 23.1 " ...
Page 170
... EC with 8x PLL MHz EC with 16x PLL MHz RC MHz XTL MHz XT MHz XT with 4x PLL MHz XT with 8x PLL MHz XT with 16x PLL MHz HS kHz LP MHz FRC internal kHz LPRC internal — See parameter OS10 for F value OSC ns See Table 23- © 2005 Microchip Technology Inc. ...
Page 171
... Mode EC 0.200 Note 1: Assumption: Oscillator Postscaler is divide Instruction Execution Cycle Time Instruction Execution Frequency: MIPS = (F cycle]. © 2005 Microchip Technology Inc. dsPIC30F3010/3011 = 2 Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) Operating temperature -40° -40° (1) (2) Min Typ Max ...
Page 172
... V = 4.5-5 +25° 3.0-3 +25° 4.5-5 +85° 3.0-3 +85° 4.5-5 +125° 4.5-5 +25° 3.0-3 +25° 4.5-5 +85° 3.0-3 +85° 4.5-5 +125° 4.5-5 +25° 3.0-3 +25° 4.5-5 +85° 3.0-3 +85° 4.5-5 +125° 4.5-5 © 2005 Microchip Technology Inc. ...
Page 173
... Frequency calibrated at 25°C and 5V. TUN bits can be used to compensate for temperature drift. TABLE 23-18: INTERNAL RC ACCURACY AC CHARACTERISTICS Param Characteristic No. (1) LPRC @ Freq = 512 kHz F20 F21 Legend: TBD = To Be Determined Note 1: Frequency at 25°C and 5V. © 2005 Microchip Technology Inc. dsPIC30F3010/3011 -40° -40° Min Typ Max Units (1) ...
Page 174
... Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) Operating temperature -40° -40° (1)(2)(3) (4) Min Typ Max — — — — — — CY Preliminary +85°C for Industrial +125°C for Extended Units Conditions ns — ns — ns — ns — . OSC © 2005 Microchip Technology Inc. ...
Page 175
... V DD SY12 MCLR Internal POR SY11 PWRT Time-out SY30 OSC Time-out Internal RESET Watchdog Timer RESET I/O Pins SY35 FSCM Delay Note: Refer to Figure 23-2 for load conditions. © 2005 Microchip Technology Inc. dsPIC30F3010/3011 SY10 SY20 SY13 Preliminary SY13 DS70141B-page 173 ...
Page 176
... User programmable s -40°C to +85° 5V, -40°C to +85° 3V, -40°C to +85° (D034) DD BOR — OSC1 period OSC s -40°C to +85°C V BGAP Band Gap Stable © 2005 Microchip Technology Inc. ...
Page 177
... Data in “Typ” column is at 5V, 25°C unless otherwise stated. FIGURE 23-7: TIMER AND 5 EXTERNAL CLOCK TIMING CHARACTERISTICS TxCK TMRX Note: Refer to Figure 23-2 for load conditions. © 2005 Microchip Technology Inc. dsPIC30F3010/3011 Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) Operating temperature -40°C T -40° ...
Page 178
... T — OSC T +85°C for Industrial A T +125°C for Extended A Max Units Conditions — ns Must also meet parameter TB15 — ns — ns Must also meet parameter TB15 — ns — prescale value (1, 8, 64, 256 — OSC © 2005 Microchip Technology Inc. ...
Page 179
... TQCP Input Period Synchronous, TQ20 T Delay from External TQCK Clock CKEXTMRL Edge to Timer Increment Note 1: These parameters are characterized but not tested in manufacturing. © 2005 Microchip Technology Inc. dsPIC30F3010/3011 Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) Operating temperature -40°C T -40°C Min ...
Page 180
... Typ Max — — Preliminary +85°C for Industrial +125°C for Extended Max Units Conditions — ns — ns — ns — ns — prescale value (1, 4, 16) +85°C for Industrial A T +125°C for Extended A Units Conditions ns — ns — © 2005 Microchip Technology Inc. ...
Page 181
... These parameters are characterized but not tested in manufacturing. 2: Data in “Typ” column is at 5V, 25°C unless otherwise stated. Parameters are for design guidance only and are not tested. © 2005 Microchip Technology Inc. dsPIC30F3010/3011 OC20 Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) ...
Page 182
... TBD TBD ns — — TBD ns — — TBD ns Preliminary T +85°C for Industrial A +125°C for Extended A Conditions -40°C to +85° -40°C to +85° -40°C to +85° -40°C to +85° -40°C to +85° -40°C to +85° © 2005 Microchip Technology Inc. ...
Page 183
... Digital Filter Note 1: These parameters are characterized but not tested in manufacturing Index Channel Digital Filter Clock Divide Select Bits. Refer to Section 16. “Quadrature Encoder Interface (QEI)” in the dsPIC30F Family Reference Manual, (DS70046). © 2005 Microchip Technology Inc. dsPIC30F3010/3011 TQ36 TQ31 TQ30 TQ35 ...
Page 184
... Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) Operating temperature -40° -40° (1) Min Max Units — — — CY Preliminary +85°C for Industrial +125°C for Extended Conditions 16, 32, 64, 128 and 256 (Note 16, 32, 64, 128 and 256 (Note 2) ns — © 2005 Microchip Technology Inc. ...
Page 185
... Data in “Typ” column is at 5V, 25°C unless otherwise stated. Parameters are for design guidance only and are not tested. 3: The minimum clock period for SCK is 100 ns. Therefore, the clock generated in Master mode must not violate this specification. 4: Assumes 50 pF load on all SPI pins. © 2005 Microchip Technology Inc. dsPIC30F3010/3011 SP10 SP21 SP20 BIT14 - - - - - -1 MSb ...
Page 186
... X data input 20 — X Preliminary SP20 SP21 -40°C T +85°C for Industrial A -40°C T +125°C for Extended A Max Units Conditions — ns — — ns — — — — — — — ns — — ns — — ns — © 2005 Microchip Technology Inc. ...
Page 187
... These parameters are characterized but not tested in manufacturing. 2: Data in “Typ” column is at 5V, 25°C unless otherwise stated. Parameters are for design guidance only and are not tested. 3: Assumes 50 pF load on all SPI pins. © 2005 Microchip Technology Inc. dsPIC30F3010/3011 SP70 SP73 SP72 MSb ...
Page 188
... SCK X (CKP = 0) SP71 SCK X (CKP = 1) MSb SDO X SDI SDI X MSb IN SP41 SP40 Note: Refer to Figure 23-2 for load conditions. DS70141B-page 186 SP70 SP73 SP35 SP72 SP52 BIT14 - - - - - -1 LSb SP30,SP31 BIT14 - - - -1 LSb IN Preliminary SP52 SP72 SP73 SP51 © 2005 Microchip Technology Inc. ...
Page 189
... The minimum clock period for SCK is 100 ns. Therefore, the clock generated in Master mode must not violate this specification. 4: Assumes 50 pF load on all SPI pins. © 2005 Microchip Technology Inc. dsPIC30F3010/3011 Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) Operating temperature (1) ...
Page 190
... C™ BUS DATA TIMING CHARACTERISTICS (MASTER MODE) IM20 SCL IM11 IM10 SDA In IM40 SDA Out Note: Refer to Figure 23-2 for load conditions. DS70141B-page 188 IM11 IM10 IM26 IM25 IM40 Preliminary IM34 IM33 Stop Condition IM21 IM33 IM45 © 2005 Microchip Technology Inc. ...
Page 191
... BRG is the value of the I C™ Baud Rate Generator. Refer to Section 21 “Inter-Integrated Circuit (I in the dsPIC30F Family Reference Manual, (DS70046 Maximum pin capacitance = 10 pF for all I © 2005 Microchip Technology Inc. dsPIC30F3010/3011 Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) Operating temperature -40° ...
Page 192
... SDA Start Condition 2 FIGURE 23-23: I C™ BUS DATA TIMING CHARACTERISTICS (SLAVE MODE) IS20 SCL IS30 IS31 SDA In IS40 SDA Out DS70141B-page 190 IS33 IS11 IS10 IS26 IS25 IS40 Preliminary IS34 Stop Condition IS21 IS33 IS45 © 2005 Microchip Technology Inc. ...
Page 193
... Clock IS45 T : Bus Free Time BF SDA IS50 C Bus Capacitive B Loading Note 1: Maximum pin capacitance = 10 pF for all I © 2005 Microchip Technology Inc. dsPIC30F3010/3011 Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) Operating temperature -40° -40° Min Max 100 kHz mode 4.7 — ...
Page 194
... CA10 CA11 CA20 Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) Operating temperature -40° -40° (1) (2) Min Typ Max — — 500 Preliminary New Value +85°C for Industrial +125°C for Extended Units Conditions ns — ns — ns — © 2005 Microchip Technology Inc. ...
Page 195
... AD23A G Gain Error ERR Legend: TBD = To Be Determined Note 1: The A/D conversion result never decreases with an increase in the input voltage, and has no missing codes. © 2005 Microchip Technology Inc. dsPIC30F3010/3011 Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) Operating temperature -40° -40° ...
Page 196
... TBD — — — 250 kHz — TBD TBD bits Preliminary +85°C for Industrial A +125°C for Extended A Conditions = 0V, INL SS REFL REFH = 0V, INL SS REFL REFH — Guaranteed dB — dB — dB — dB — dB — dB — — — © 2005 Microchip Technology Inc. ...
Page 197
... MCU Family Reference Manual, (DS70046), Section 17, “10-bit A/D Converter”. SAMP 3 - Software clears ADCON. SAMP to start conversion Sampling ends, conversion sequence starts Convert bit Convert bit Convert bit One T for end of conversion. AD © 2005 Microchip Technology Inc. dsPIC30F3010/3011 AD55 Preliminary ...
Page 198
... Convert bit 8. DS70141B-page 196 AD55 AD55 Convert bit One Begin conversion of next channel 8 - Sample for time specified by SAMC described in the dsPIC30F SAMP Family Reference Manual, (DS70046), Section 17, “10-bit A/D Converter”. Preliminary T SAMP T CONV for end of conversion. © 2005 Microchip Technology Inc. ...
Page 199
... Legend: TBD = To Be Determined Note 1: Because the sample caps will eventually lose charge, clock periods above 100 sec can affect linearity performance, especially at elevated temperatures. © 2005 Microchip Technology Inc. dsPIC30F3010/3011 Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) Operating temperature -40° ...
Page 200
... NOTES: DS70141B-page 198 Preliminary © 2005 Microchip Technology Inc. ...