ADUC7024BST62-REEL Analog Devices Inc, ADUC7024BST62-REEL Datasheet - Page 22

• Manufacturer Part Number: ADUC7024BST62-REEL
• Description: IC MCU FLASH 62K W/ANLG 64-LQFP
• Manufacturer: Analog Devices Inc
• Series: MicroConverter® ADuC7xxxr

Specifications of ADUC7024BST62-REEL

• Rohs Status: RoHS non-compliant
• Design Resources: Sensing Low-g Acceleration Using ADXL345 Digital Accelerometer Connected to ADuC7024 (CN0133)
• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 44MHz
• Connectivity: EBI/EMI, I²C, SPI, UART/USART
• Peripherals: PLA, PWM, PSM, Temp Sensor, WDT
• Number Of I /o: 30
• Program Memory Size: 62KB (62K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 10x12b; D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 64-LQFP
• Eeprom Size: -
• Other names: ADUC7024BST62REEL

ADuC7019/20/21/22/24/25/26/27/28/29
Table 12. Pin Function Descriptions (ADuC7024/ADuC7025 64-Lead LFCSP_VQ and 64-Lead LQFP)
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
Mnemonic
ADC4
ADC5
ADC6
ADC7
ADC8
ADC9
GND
ADCNEG
DAC0/ADC12
DAC1/ADC13
TMS
TDI
P4.6/PLAO[14]
P4.7/PLAO[15]
BM/P0.0/CMP
P0.6/T1/MRST/PLAO[3]
TCK
TDO
IOGND
IOV
LV
DGND
P3.0/PWM0
P3.1/PWM0
P3.2/PWM1
P3.3/PWM1
P0.3/TRST/ADC
RST
P3.4/PWM2
P3.5/PWM2
IRQ0/P0.4/PWM
IRQ1/P0.5/ADC
P2.0/SPM9/PLAO[5]/CONV
P0.7/ECLK/XCLK/SPM8/PLAO[4]
XCLKO
XCLKI
DD
DD
REF
H
L
H
L
H
L
/PLAI[9]
/PLAI[11]
/PLAI[13]
/PLAI[8]
/PLAI[10]
/PLAI[12]
OUT
BUSY
BUSY
TRIP
/PLAI[7]
/PLAO[2]
/PLAO[1]
START
Description
Single-Ended or Differential Analog Input 4.
Single-Ended or Differential Analog Input 5.
Single-Ended or Differential Analog Input 6.
Single-Ended or Differential Analog Input 7.
Single-Ended or Differential Analog Input 8.
Single-Ended or Differential Analog Input 9.
Ground Voltage Reference for the ADC. For optimal performance, the analog power supply
should be separated from IOGND and DGND.
Bias Point or Negative Analog Input of the ADC in Pseudo Differential Mode. Must be connected
to the ground of the signal to convert. This bias point must be between 0 V and 1 V.
DAC0 Voltage Output/Single-Ended or Differential Analog Input 12. DAC outputs are not present
on the ADuC7025.
DAC1 Voltage Output/Single-Ended or Differential Analog Input 13. DAC outputs are not present
on the ADuC7025.
JTAG Test Port Input, Test Mode Select. Debug and download access.
JTAG Test Port Input, Test Data In. Debug and download access
General-Purpose Input and Output Port 4.6/Programmable Logic Array Output Element 14.
General-Purpose Input and Output Port 4.7/Programmable Logic Array Output Element 15.
Multifunction I/O Pin. Boot mode. The ADuC7024/ADuC7025 enter download mode if BM is low at
reset and execute code if BM is pulled high at reset through a 1 kΩ resistor/General-Purpose Input
and Output Port 0.0/Voltage Comparator Output/Programmable Logic Array Input Element 7.
Multifunction Pin, Driven Low After Reset. General-Purpose Output Port 0.6/Timer1 Input/Power-
On Reset Output/Programmable Logic Array Output Element 3.
JTAG Test Port Input, Test Clock. Debug and download access.
JTAG Test Port Output, Test Data Out. Debug and download access.
Ground for GPIO (see Table 78). Typically connected to DGND.
3.3 V Supply for GPIO (see Table 78) and Input of the On-Chip Voltage Regulator.
2.6 V Output of the On-Chip Voltage Regulator. This output must be connected to a 0.47 μF
capacitor to DGND only.
Ground for Core Logic.
General-Purpose Input and Output Port 3.0/PWM Phase 0 High-Side Output/Programmable Logic
Array Input Element 8.
General-Purpose Input and Output Port 3.1/PWM Phase 0 Low-Side Output/Programmable Logic
Array Input Element 9.
General-Purpose Input and Output Port 3.2/PWM Phase 1 High-Side Output/Programmable Logic
Array Input Element 10.
General-Purpose Input and Output Port 3.3/PWM Phase 1 Low-Side Output/Programmable Logic
Array Input Element 11.
General-Purpose Input and Output Port 0.3/JTAG Test Port Input, Test Reset/ADC
Reset Input, Active Low.
General-Purpose Input and Output Port 3.4/PWM Phase 2 High-Side Output/Programmable Logic
Array Input 12.
General-Purpose Input and Output Port 3.5/PWM Phase 2 Low-Side Output/Programmable Logic
Array Input Element 13.
Multifunction I/O Pin. External Interrupt Request 0, Active High/General-Purpose Input and
Output Port 0.4/PWM Trip External Input/Programmable Logic Array Output Element 1.
Multifunction I/O Pin. External Interrupt Request 1, Active High/General-Purpose Input and
Output Port 0.5/ADC
Serial Port Multiplexed. General-Purpose Input and Output Port 2.0/UART/Programmable Logic
Array Output Element 5/Start Conversion Input Signal for ADC.
Serial Port Multiplexed. General-Purpose Input and Output Port 0.7/Output for External Clock
Signal/Input to the Internal Clock Generator Circuits/UART/Programmable Logic Array Output
Element 4.
Output from the Crystal Oscillator Inverter.
Input to the Crystal Oscillator Inverter and Input to the Internal Clock Generator Circuits.
Rev. C | Page 22 of 96
BUSY
Signal Output/Programmable Logic Array Output Element 2.
BUSY
Signal Output.