Z8F3202VS020EC Zilog, Z8F3202VS020EC Datasheet - Page 14

• Manufacturer Part Number: Z8F3202VS020EC
• Description: IC ENCORE MCU FLASH 32K 68PLCC
• Manufacturer: Zilog
• Series: Encore!®r

Specifications of Z8F3202VS020EC

• Core Processor: Z8
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C, IrDA, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 46
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 68-LCC (J-Lead)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Other names: 269-3177

Table 3. Z8F6403 Errata for Devices with Date Codes 0226 and Earlier (Continued)
UP004207-0308
Sl
No
7
8
9
Summary
Port H alternate
function forces pins
to output.
Extraneous register
reads by the eZ8
CPU.
UART Overrun
errors may be
missed.
Errata to Z8F640x, Z8F480x, Z8F320x, Z8F240x, Z8F160x (Z8 Encore!
Description
When the alternate function for Port H is enabled, the Port H pins are
configured as outputs.
Workaround
Do not enable the Port H alternate function when using the Port H ADC inputs.
These pins continue to function properly as ADC inputs even though not
configured for alternate function. For ADC operation configure the Port H pins
as inputs.
There are several instructions during which the CPU performs extra register
reads. Most are addresses the CPU was trying to read, the CPU reads the
same register twice. There are a couple instructions where the CPU reads
from random addresses. This is typically not a problem, unless the register
being read is affected by a read operation. The registers affected by read
operations including the WDTCTL register are the UART, SPI, and I
Receive Data registers. If a read occurs on these registers, receive characters
may be lost or the WDT status lost.
Workaround
Do not set RP to %XF.
Also, only use the LDX instruction on peripheral registers affected by read
operations.
Framing Error, Parity Error, Break Detect, and Rx Overrun Error conditions are
cleared up on reading the UART Receive Data register. During the time
between reading the UART Status register and the UART Receive Data
register, it is possible for another character to be received. This causes all
UART error flags and the UART Receive Data register to be updated with the
new character, making it is possible to miss the Overrun Error.
The window for this error only occurs if a UART Overrun Error occurs between
the time the UART Status register is read and the UART Receive Data register
is read. If vectored interrupts are used, service the UART. Receiver Overrun
conditions should not occur thereafter.
If you have long ISR or are polling the UART instead of using vectored inter-
rupts, Overrun errors become more likely. The window for this problem to
occur is small, yet becomes more probable if UART Receiver Overrun condi-
tions occur frequently.
Workaround
When the user code employs vectored interrupts for the UART and does not
have long ISR, this is not a problem. Even for long ISR, the problem can be
avoided by,
•
•
Nesting the ISR
Adjusting the interrupt masks and re-enabling interrupts
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