Z8F3202VS020EC Zilog, Z8F3202VS020EC Datasheet - Page 7

• Manufacturer Part Number: Z8F3202VS020EC
• Description: IC ENCORE MCU FLASH 32K 68PLCC
• Manufacturer: Zilog
• Series: Encore!®r

Specifications of Z8F3202VS020EC

• Core Processor: Z8
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C, IrDA, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 46
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 68-LCC (J-Lead)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Other names: 269-3177

Z8F640x, Z8F480x, Z8F320x, Z8F240x, Z8F160x with QUAL Topmark
The errata listed in
and later, where the date code is YYWW (year and week of assembly).When reviewing the following
errata, refer to the most recent version of the product specification. Data contained in this document is
Preliminary only.
Table 2. Z8F640x, Z8F480x, Z8F320x, Z8F240x, Z8F160x Errata for Devices with Date
UP004207-0308
Sl
No
1
2
3
Summary
The OCD’s Step,
Stuff, and Execute
instructions do not
work properly if an
interrupt is pending.
Extraneous register
reads by the eZ8
CPU.
SPI does not
support single bit
data transfers.
Codes 0239 and Later
Table 2
Errata to Z8F640x, Z8F480x, Z8F320x, Z8F240x, Z8F160x (Z8 Encore!
are found in the Z8F640x products with a QUAL topmark and date codes 0239
Description
The OCD’s Step, Stuff, and Execute instructions do not work if an interrupt is
pending. When in DEBUG mode, the eZ8 CPU will not acknowledge interrupts
or DMA requests. However, if an interrupt or DMA request is pending, the eZ8
CPU will not acknowledge an instruction. If an interrupt is pending and an
OCD Step, Stuff, or Execute instruction is executed, the Debugger will wait for-
ever for the eZ8 CPU to acknowledge the opcode because of the pending
interrupt.
Workaround
The OCD must look at the next instruction before single stepping and take
appropriate measures. Instead of executing the EI instruction, rewrite the PC
to the instruction following the EI and then enable interrupts through a register
write to the interrupt control register.
There are several instructions during which the CPU performs extra register
reads. Most are addresses the CPU was trying to read, the CPU reads the
same register twice. There are a couple instructions where the CPU reads
from random addresses. This is typically not a problem, unless the register
being read is affected by a read operation. The registers affected by read
operations include the WDTCTL and DMAA_STAT registers and the UART,
SPI, and I
receive characters may be lost or the WDT status lost.
Workaround
Do not set RP to %XF.
Also, only use the LDX instruction on peripheral registers affected by read
operations.
The SPI does not function properly when configured for single-bit data
transfers. This is not a typical SPI data format.
Workaround
None.
2
C Receive Data registers. If a read occurs on these registers,
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