ZGP323HAP4016G Zilog, ZGP323HAP4016G Datasheet
ZGP323HAP4016G
Specifications of ZGP323HAP4016G
ZGP323HAP4016G
Related parts for ZGP323HAP4016G
ZGP323HAP4016G Summary of contents
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... Microcontrollers ZGP323H OTP MCU Family Product Specification PS023807-0707 ® Copyright ©2007 by Zilog , Inc. All rights reserved. www.zilog.com ...
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... TECHNOLOGY DESCRIBED HEREIN OR OTHERWISE. The information contained within this document has been verified according to the general principles of electrical and mechanical engineering. Z8, Z8 GP, Z8 Encore!, and ZNEO are trademarks or registered trademarks of Zilog, Inc. All other product or service names are the property of their respective owners. ...
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Revision History Each instance in the Revision History table reflects a change to this document from its previous revision. For more details, refer to the corresponding pages or appropriate link in the table below. Revision Date Level Description July 07 ...
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Table of Contents Architectural Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Packaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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... Architectural Overview Zilog’s ZGP323H is an OTP-based member of the MCU family of infrared microcontrollers. With 237 B of general-purpose RAM and OTP, Zilog’s CMOS microcontrollers offer fast-executing, efficient use of memory, sophisticated interrupts, input/output bit manipulation capabilities, automated pulse generation/ reception, and internal key-scan pull-up transistors. ...
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Development Features Table 2 lists the features of ZGP323H members. Table 2. Features Device ZGP323H OTP MCU Family • Low power consumption—18 mW (typical) • Temperature S = Standard 0 °C to +70 ° Extended -40 ...
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Port 0: 0–3 pull-up transistors – Port 0: 4–7 pull-up transistors – Port 1: 0–3 pull-up transistors – Port 1: 4–7 pull-up transistors – Port 2: 0–7 pull-up transistors – EPROM Protection – WDT enabled at POR – Functional Block ...
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SCLK Clock Divider Edge Input Glitch Detect Filter Circuit PS023807-0707 HI16 LO16 8 8 16-Bit T16 TC16H TC16L HI8 LO8 8 8 8-Bit TC8H TC8L Figure 2. Counter/Timers Diagram Product ...
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... The pin configuration for the 20-pin PDIP/SOIC/SSOP is illustrated in described in Table in Figure 4 and described in 48-pin SSOP versions are illustrated in For customer engineering code development erasable windowed cerdip packaging is offered in 20-pin, 28-pin, and 40-pin configurations. Zilog guarantee these packages for use in production. P25 P26 P27 P07 V XTAL2 ...
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Table 3. 20-Pin PDIP/SOIC/SSOP/CDIP* Pin Identification (Continued) Pin No Symbol 14 P01 15 V 16–20 P20–P24 XTAL2 XTAL1 Figure 4. 28-Pin PDIP/SOIC/SSOP/CDIP* Pin Configuration Table 4. 28-Pin PDIP/SOIC/SSOP/CDIP* Pin Identification Pin No Symbol 1-3 P25-P27 4-7 P04-P07 ...
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... P20-P24 XTAL2 XTAL1 Figure 5. 40-Pin PDIP/CDIP* Pin Configuration Note: *Windowed Cerdip. These units are intended to be used for engineering code development ® only. Zilog does not recommend/guarantee this package for production use. PS023807-0707 Direction Description Input/Output Port 0, Bits Ground Input/Output ...
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NC P25 P26 P27 P04 N/C P05 P06 P14 P15 P07 VDD VDD N/C P16 P17 XTAL2 XTAL1 P31 P32 P33 P34 NC VSS Figure 6. 48-Pin SSOP Pin Configuration Table 5. 40- and 48-Pin Configuration 40-Pin PDIP # 26 ...
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Table 5. 40- and 48-Pin Configuration (Continued) 40-Pin PDIP # PS023807-0707 ...
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Table 5. 40- and 48-Pin Configuration (Continued) 40-Pin PDIP # Pin Functions XTAL1 Crystal 1 (Time-Based Input) This pin connects a parallel-resonant crystal or ceramic resonator to the on-chip oscillator input. Additionally, an optional external single-phase clock can be coded ...
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ONE floating port and will read back as ZERO. The following instruction will set P00-P07 all LOW. AND P0,#%F0 Port 0 (P07–P00) Port 8-bit, bidirectional, CMOS-compatible port. These eight I/O ...
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Z8 GP OTP Open-Drain I/O Out In Port 1 (P17–P10) Port 1 (see Figure After POR, Port 1 is configured as an input port. The output drivers are either push-pull or open-drain and are controlled by bit D1 in the ...
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Z8 GP OTP Open-Drain OEN Out In Port 2 (P27–P20) Port 8-bit, bidirectional, CMOS-compatible I/O port (see lines can be independently configured under software control as inputs or outputs. Port 2 is always available for I/O operation. ...
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Z8 GP OTP Open-Drain I/O Out In Port 3 (P37–P30) Port 8-bit, CMOS-compatible fixed I/O port (see fixed input (P33–P30) and four fixed output (P37–P34), which can be configured under software control for interrupt and as output ...
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Z8 GP OTP P31 (AN1) Pref1 P32 (AN2) P33 (REF2) From Stop Mode Recovery Source of SMR Two on-board comparators process analog signals on P31 and P32, with reference to the voltage on Pref1 and P33. The analog function is ...
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Note: Comparators are powered down by entering STOP Mode. For P31–P33 to be used in a Stop Mode Recovery (SMR) source, these inputs must be placed into digital mode. 2 Table 6. Port 3 Pin Function Summary Pin I/O Pref1/P30 ...
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P34 T8_Out P31 P31 + - P30 (Pref1) P32 P32 + - P33 Figure 11. Port 3 Counter/Timer Output Configuration PS023807-0707 CTR0, D0 PCON MUX P3M D1 Comp1 CTR2, D0 Out 35 MUX T16_Out CTR1, D6 ...
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Comparator Inputs In analog mode, P31 and P32 have a comparator front end. The comparator reference is supplied to P33 and Pref1. In this mode, the P33 internal data latch and its corresponding IRQ1 are diverted to the SMR sources ...
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Functional Description This device incorporates special functions to enhance the Z8 functionality in consumer and battery-operated applications. Program Memory This device addresses OTP memory. The first 12 Bytes are reserved for interrupt vectors. These locations ...
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Location of first Byte of instruction executed after RESET Interrupt Vector (Lower Byte) Interrupt Vector (Upper Byte) Figure 12. Program Memory Map (32 K OTP) Expanded Register File The register file has been expanded to allow for additional system control ...
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Bits 7–4 of register RP select the working register group. Bits 3–0 of register RP select the expanded register file bank. Note: An expanded register bank is also referred expanded register group (see Figure 13). PS023807-0707 ZGP323H ...
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Register Pointer Working Register Group Pointer Register File (Bank 0)** Expanded Reg. Bank 0/Group ( (0) ...
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The upper nibble of the register pointer (see group bytes in the register file, is accessed out of the possible 256. The lower nibble selects the expanded register file bank and, in the case of the Z8 GP ...
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LD LD for access to bank D register group 0) LD expanded register bank D and working group 7 of bank 0 for access CTRL2→register 71h LD ; CTRL2→register 71h Register File The register file (bank 0) consists ...
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Stack The internal register file is used for the stack. An 8-bit Stack Pointer SPL (R255) is used for the internal stack that resides in ...
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Timers T8_Capture_HI—HI8(D)0BH This register holds the captured data from the output of the 8-bit Counter/Timer0. Typically, this register holds the number of counts when the input signal is 1. Field T8_Capture_HI T8_Capture_LO—L08(D)0AH This register holds the captured data from the ...
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Counter/Timer2 LS-Byte Hold Register—TC16L(D)06H Field T16_Data_LO Counter/Timer8 High Hold Register—TC8H(D)05H Field T8_Level_HI Counter/Timer8 Low Hold Register—TC8L(D)04H Field T8_Level_LO CTR0 Counter/Timer8 Control Register—CTR0(D)00H Table 7 lists and briefly describes the fields for this register. Table 7. CTR0(D)00H Counter/Timer8 Control Register Field ...
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Table 7. CTR0(D)00H Counter/Timer8 Control Register (Continued) Field Bit Position Counter_INT_Mask ------1- P34_Out -------0 Note: * Indicates the value upon Power-On Reset. * *Indicates the value upon Power-On Reset. Not reset with a Stop Mode Recovery. T8 Enable This field ...
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Counter_INT_Mask Set this bit to allow an interrupt when T8 has a timeout. P34_Out This bit defines whether P34 is used as a normal output pin or the T8 output. T8 and T16 Common Functions—CTR1(0D)01H This register controls the functions ...
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Table 8. CTR1(0D)01H T8 and T16 Common Functions (Continued) Field Bit Position Initial_T8_Out/ ------1- Rising Edge Initial_T16_Out/ -------0 Falling_Edge Note: * Default at Power-On Reset * Default at Power-On Reset. Not reset with Stop Mode Recovery. Mode If the result ...
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Transmit_Submode/Glitch Filter In TRANSMIT Mode, this field defines whether T8 and T16 are in the PING-PONG mode or in independent normal operation mode. Setting this field to NORMAL OPERA- TION Mode terminates the PING-PONG Mode operation. When set to 10, ...
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Table 9. CTR2(D)02H: Counter/Timer16 Control Register Field Bit Position T16_Enable 7------- Single/Modulo-N -6------ Time_Out --5----- T16 _Clock ---43--- Capture_INT_Mask -----2-- Counter_INT_Mask ------1- P35_Out -------0 Note: * Indicates the value upon Power-On Reset. ** Indicates the value upon Power-On Reset. Not ...
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In DEMODULATION Mode, when set to 0, T16 captures and reloads on detection of all the edges. When set to 1, T16 captures and detects on the first edge but ignores the subse- quent edges. For details, see description of ...
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Table 10. CTR3 (D)03H: T8/T16 Control Register (Continued) Field Bit Position Reserved ---43210 * Indicates the value on Power-On Reset. ** Indicates the value on Power-On Reset. Not reset with a Stop Mode Recovery. Counter/Timer Functional Blocks Input Circuit The ...
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Reset T8_Enable Bit Set Timeout Status Bit (CTR0 D5) and Generate Timeout_Int if Enabled Figure 17. TRANSMIT Mode Flowchart PS023807-0707 T8 (8-Bit) TRANSMIT Mode No T8_Enable Bit Set CTR0, D7 Yes 0 CTR1, D1 Value Load TC8L Set T8_OUT Reset ...
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When T8 is enabled, the output T8_OUT switches to the initial value (CTR1, D1). If the initial value (CTR1, D1 TC8L is loaded; otherwise, TC8H is loaded into the counter. In SINGLE-PASS Mode (CTR0, D6), T8 counts down ...
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Caution: Using the same instructions for stopping the counter/timers and setting the status bits is not recommended. Two successive commands are necessary. First, the counter/timers must be stopped. Second, the status bits must be reset. These commands are required as ...
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Meanwhile loaded with status bit (CTR0, D5) is set, and an interrupt can be generated if enabled (CTR0, D1). T8 then continues counting from Positive Figure 21. DEMODULATION Mode Count Capture Flowchart PS023807-0707 and starts counting again. If ...
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Disable TC8 Figure 22. DEMODULATION Mode Flowchart PS023807-0707 T8 (8-Bit) Mode DEMODULATION T8 Enable CTR0 Yes → TC8 FFH First Edge Present No Yes Enable TC8 T8_Enable Bit Set No Yes No Edge Present Yes T8 Timeout Set ...
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T16 TRANSMIT Mode In NORMAL or PING-PONG mode, the output of T16 when not enabled, is dependent on CTR1, D0 T16_OUT T16_OUT is 0. You can force ...
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Do not load these registers at the time the values are to be loaded into the counter/timer Caution: to ensure known operation. An initial count not allowed. An initial count of 0 causes T16 to count from ...
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CTR2 Is 1 T16 ignores the subsequent edges in the input signal and continues counting down. A tim- eout of T8 causes T16 to capture its current value and generate an interrupt if enabled (CTR2, D2). In ...
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Initiating PING-PONG Mode First, ensure both counter/timers are not running. Set T8 into SINGLE-PASS mode (CTR0, D6), set T16 into SINGLE-PASS mode (CTR2, D6), and set the PING-PONG mode (CTR1, D2; D3). These instructions can be in random order. Finally, ...
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During PING-PONG Mode The enable bits of T8 and T16 (CTR0, D7; CTR2, D7) are set and cleared alternately by hardware. The timeout bits (CTR0, D5; CTR2, D5) are set every time the counter/timers reach the terminal count. Interrupts The ...
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IRQ Register D6, D7 IRQ2 Interrupt Request PS023807-0707 Stop Mode Recovery Source P33 0 P31 P32 Interrupt Edge Timer 16 Select IRQ0 IRQ1 IRQ3 IRQ IMR IPR Global Interrupt Enable Priority Logic Vector Select Figure 28. Interrupt Block Diagram ZGP323H ...
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Table 11. Interrupt Types, Sources, and Vectors Name Source IRQ0 P32 IRQ1 P33 IRQ2 P31, T IRQ3 T16 IRQ4 T8 IRQ5 LVD When more than one interrupt is pending, priorities are resolved by a programmable prior- ity encoder controlled by ...
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... MHz * Preliminary value including pin parasitics Zilog’s ZGP323H supports crystal, resonator, and oscillator. Most resonators have a fre- quency tolerance of less than +/-0.5% which is adequate for remote control applications. The typical resonator has a very fast start up time on the order of a few hundred microsec- onds ...
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STOP mode. The STOP mode recovery delay must be selected (bit 5 of SMR = 1) if resonator or crystal is used as clock source. For both resonator and crystal oscillation, the oscillation ground ...
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Port Configuration Register The Port Configuration (PCON) register Port located in the expanded register 2 at Bank F, location 00. PCON(FH)00H Default setting after reset. Figure 30. Port Configuration Register (PCON) (Write Only) ...
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XOR-gate input is required from the recovery source. Bit 5 controls the reset delay after recovery. Bits D2, D3, and D4 of the SMR register specify the source of ...
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HALT Mode (where TCLK sources interrupt logic). After Stop Mode Recovery, this bit is set OSC ÷ 2 ÷ 16 Stop Mode Recovery Source (D2, D3, and D4) These three bits of the SMR ...
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Table 13. SMR2(F)0DH:Stop Mode Recovery Register 2* (Continued) Field Bit Position Source ---432-- Reserved ------10 Notes: * Port pins configured as outputs are ignored as a SMR recovery source. † Indicates the value upon Power-On Reset. PS023807-0707 Value Description † ...
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SMR VCC SMR P31 SMR P32 SMR P33 SMR P27 SMR P20 P23 SMR P20 P27 SMR D6 To ...
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Table 14. Stop Mode Recovery Source SMR:432 Note: Any Port 2 bit defined ...
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Stop Mode Recovery Register 2 (SMR2) This register determines the mode of Stop Mode Recovery for SMR2 SMR2(0F) Note: If used in conjunction with SMR, either of the two specified events causes a Stop ...
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Watchdog Timer Mode Register (WDTMR) The Watchdog Timer (WDT retriggerable one-shot timer that resets the Z8 reaches its terminal count. The WDT must initially be enabled by executing the WDT instruction. On subsequent executions of the WDT instruction, ...
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Table 15. Watchdog Timer Time Select WDTMR During Halt (D2) This bit determines whether or not the WDT is active during HALT Mode indicates active during HALT. The ...
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WDTMR During STOP (D3) This bit determines whether or not the WDT is active during STOP Mode. Because the XTAL clock is stopped during STOP Mode, the on-board RC has to be selected as the clock source to the WDT/POR ...
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Field Bit Position LVD 76543--- -----2-- ------1- -------0 * Default after POR. Note: Do not modify register P01M while checking a low-voltage condition. Switching noise of both ports 0 and 1 together might trigger the LVD flag. Voltage Detection and ...
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CTR0(0D)00H Default setting after reset Default setting after Reset. Not reset with a Stop Mode Recovery. Figure 37. TC8 Control Register ((0D)O0H: Read/Write Except Where Noted) PS023807-0707 ZGP323H Product ...
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CTR1(0D)01H PS023807-0707 ZGP323H Product Specification TRANSMIT Mode* R/W 0 T16_OUT is 0 initially 1 T16_OUT is 1 initially DEMODULATION Mode Falling Edge Detection R 1 Falling Edge Detection W ...
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CTR1(0D)01H * Default setting after Reset. ** Default setting after Reset. Not reset with a Stop Mode Recovery. Figure 38. T8 and T16 Common Control Functions ((0D)01H: Read/Write) Notes: Take care in differentiating the TRANSMIT Mode from DEMODULATION Mode. Depend- ...
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Default setting after Reset. ** Default setting after Reset. Not reset with a Stop Mode Recovery. Figure 39. T16 Control Register ((0D) 2H: Read/Write Except Where Noted) CTR3(0D)03H Default setting after reset. ** Default setting ...
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LVD(0D)0CH Default setting after reset. Note: Do not modify register P01M while checking a low-voltage condition. Switching noise of both ports 0 and 1 together might trigger the LVD flag. Expanded Register File Control Registers (0F) ...
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Default setting after reset. Figure 42. Port Configuration Register (PCON)(0F)00H: Write Only) SMR(0F)0BH PS023807-0707 ZGP323H Product Specification Comparator Output Port 3 0 P34, P37 Standard Output * 1 P34, P37 Comparator ...
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Default setting after reset Set after Stop Mode Recovery the XOR gate input Default setting after reset. Must using a crystal or resonator clock source. * ...
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SMR2(0F)0DH Note: If used in conjunction with SMR, either of the two specified events causes a Stop Mode Recovery. * Default setting after reset. Not reset with a Stop Mode Recovery ...
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WDTMR(0F)0FH Default setting after reset. Not reset with a Stop Mode Recovery. Figure 45. Watchdog Timer Register ((0F) 0FH: Write Only) Standard Control Registers R246 P2M(F6H Default setting after reset. Not reset ...
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R247 P3M(F7H Default setting after reset. Not reset with a Stop Mode Recovery. Figure 47. Port 3 Mode Register (F7H: Write Only) R248 P01M(F8H PS023807-0707 ...
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Default setting after reset; only P00, P01 and P07 are available on 20-pin configurations. Figure 48. Port 0 and 1 Mode Register (F8H: Write Only) R249 IPR(F9H PS023807-0707 ZGP323H Product Specification ...
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Figure 49. Interrupt Priority Register (F9H: Write Only) R250 IRQ(FAH Figure 50. Interrupt Request Register (FAH: Read/Write) PS023807-0707 ZGP323H Product Specification IRQ1, IRQ4, Priority (Group C) 0: IRQ1 > IRQ4 1: IRQ4 ...
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R251 IMR(FBH Default setting after reset Only by using EI, DI instruction required before changing the IMR register. Figure 51. Interrupt Mask Register (FBH: Read/Write) R252 Flags(FCH Figure 52. ...
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R253 RP(FDH Default setting after reset = 0000 0000 Figure 53. Register Pointer (FDH: Read/Write) R254 SPH(FEH Figure 54. Stack Pointer High (FEH: Read/Write) R255 SPL(FFH Figure 55. Stack Pointer Low ...
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Electrical Characteristics Absolute Maximum Ratings Stresses greater than those listed in This rating is a stress rating only. Functional operation of the device at any condition above those indicated in the operational sections of these specifications is not implied. Exposure ...
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From Output Under Test Capacitance Table 18 lists the capacitances. Table 18. Capacitance Parameter Input capacitance Output capacitance I/O capacitance Note ° Characteristics Table 19. GP323HS DC Characteristics Symbol Parameter V V Supply Voltage ...
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Table 19. GP323HS DC Characteristics (Continued) Symbol Parameter V V Output High Voltage 2.0-5.5 OH2 (P36, P37, P00, P01) V Output Low Voltage 2.0-5.5 OL1 V Output Low Voltage 2.0-5.5 OL2 (P00, P01, P36, P37) V Comparator Input 2.0-5.5 OFFSET ...
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Table 19. GP323HS DC Characteristics (Continued) Symbol Parameter Low Voltage BO CC Protection V V Low-Voltage LVD CC Detection V Vcc High-Voltage HVD Detection Notes: 1. All outputs unloaded, inputs at rail. 2. CL1 = CL2 = ...
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Table 20. GP323HE DC Characteristics (Continued) Symbol Parameter V I Input Leakage 2.0-5 Pull-up Resistance 2 3 Output Leakage 2.0-5 Supply Current 2 3 ...
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Table 20. GP323HE DC Characteristics (Continued) Symbol Parameter V Notes: 1. All outputs unloaded, inputs at rail. 2. CL1 = CL2 = 100 pF. 3. Oscillator stopped. 4. Oscillator stops when V falls below strongly ...
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Table 21. GP323HA DC Characteristics (Continued) Symbol Parameter V I Supply Current 2 3 Standby Current 2.0 V CC1 (HALT Mode) 3 Standby Current 2.0 V CC2 (STOP Mode) 3.6 ...
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Table 22. EPROM/OTP Characteristics Symbol Parameter Erase Time Data Retention @ use years Program/Erase Endurance Notes: 1. For windowed cerdip package only. 2. Standard: 0 ° °C; Extended: -40 °C to +105 °C; Automotive: -40 °C to +125 ...
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AC Characteristics Figure 57 and Table 23 Clock IRQ N Clock Setup Stop Mode Recovery Source PS023807-0707 describe the Alternating Current (AC) characteristics Figure 57. AC Timing ...
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Table 23. AC Characteristics No Symbol Parameter 1 TpC Input Clock Period 2.0–5.5 2 TrC,TfC Clock Input Rise and Fall Times 3 TwC Input Clock Width 4 TwTinL Timer Input Low Width 5 TwTinH Timer Input High Width 6 TpTin ...
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Packaging Package information for all versions of ZGP323H is depicted in Figure 68. PS023807-0707 Figure 58. 20-Pin CDIP Package ZGP323H Product Specification 84 Figures 59 through Packaging ...
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Figure 59. 20-Pin PDIP Package Diagram Figure 60. 20-Pin SOIC Package Diagram PS023807-0707 ZGP323H Product Specification 85 Packaging ...
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Figure 61. 20-Pin SSOP Package Diagram PS023807-0707 ZGP323H Product Specification 86 Packaging ...
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Figure 62. 28-Pin SOIC Package Diagram PS023807-0707 ZGP323H Product Specification 87 Packaging ...
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Figure 63. 28-Pin CDIP Package Diagram Figure 64. 28-Pin PDIP Package Diagram PS023807-0707 ZGP323H Product Specification 88 Packaging ...
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DETAIL SEATING PLANE Figure 65. 28-Pin SSOP Package Diagram Figure 66. 40-Pin PDIP Package Diagram PS023807-0707 C MILLIMETER SYMBOL MIN NOM A 1.73 1.86 A1 0.05 0. ...
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Figure 67. 40-Pin CDIP Package Diagram PS023807-0707 ZGP323H Product Specification 90 Packaging ...
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... Figure 68. 48-Pin SSOP Package Design Note: Check with Zilog assembly. PS023807-0707 Detail SEATING PLANE L 0-8˚ ® on the actual bonding diagram and coordinate for chip-on-board ZGP323H Product Specification CONTROLLING DIMENSIONS : MM LEADS ARE COPLANAR WITHIN .004 INCH Packaging 91 ...
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Ordering Information 32 KB Standard Temperature: 0 °C to +70 °C Part Number Description ZGP323HSH4832G 48-pin SSOP 32K OTP ZGP323HSP4032G 40-pin PDIP 32K OTP ZGP323HSK2832E 28-pin CDIP 32K OTP ZGP323HSK4032E 40-pin CDIP 32K OTP ZGP323HSH2832G 28-pin SSOP 32K OTP ZGP323HSP2832G ...
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... KB Automotive Temperature: –40 °C to +125 °C Part Number Description ZGP323HAH4816G 48-pin SSOP 16K OTP ZGP323HAS2816G 28-pin SOIC 16K OTP ZGP323HAP4016G 40-pin PDIP 16K OTP ZGP323HAH2816G 28-pin SSOP 16K OTP ZGP323HAP2016G 20-pin PDIP 16K OTP ZGP323HAP2816G 28-pin PDIP 16K OTP PS023807-0707 ...
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KB Standard Temperature: 0 °C to +70 °C Part Number Description ZGP323HSH4808G 48-pin SSOP 8K OTP ZGP323HSP4008G 40-pin PDIP 8K OTP ZGP323HSH2808G 28-pin SSOP 8K OTP ZGP323HSP2808G 28-pin PDIP 8K OTP 8 KB Extended Temperature: –40 °C to +105 ...
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... ZGP323HAP4004G 40-pin PDIP 4K OTP ZGP323HAH2804G 28-pin SSOP 4K OTP ZGP323HAP2804G 28-pin PDIP 4K OTP Additional Components Part Number Description ® Visit the Zilog web site at and development tools for the ZGP323H. PS023807-0707 Part Number ZGP323HSS2804G 28-pin SOIC 4K OTP ZGP323HSH2004G 20-pin SSOP 4K OTP ZGP323HSP2004G 20-pin PDIP 4K OTP ...
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... For fast results, contact your local Zilog desired. Codes ZG = Zilog General-Purpose Family P = OTP 323 = Family Designation H = High Voltage T = Temparature S = Standard 0 °C to +70 ° Extended -40 °C to +105 ° Automotive -40 °C to +125 ° Package Type CDIP P = PDIP H = SSOP S = SOIC ## = Number of Pins CC = Memory Size ...
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... Example ZG P 323 PS023807-0707 ZGP323H Product Specification Molding Compound Memory Size Number of Pins Package Type CDIP P = PDIP H = SSOP S = SOIC Temperature Standard E = Extended A = Automotive Voltage High Family Designation OTP ® Zilog General-Purpose Family Ordering Information 97 ...
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Index Numerics 16-bit counter/timer circuits 40 20-pin DIP package diagram 85 20-pin SSOP package diagram 86 28-pin DIP package diagram 88 28-pin SOIC package diagram 87 28-pin SSOP package diagram 89 40-pin DIP package diagram 89 48-pin SSOP package diagram ...
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D DC characteristics 75 demodulation mode count capture flowchart 38 flowchart 39 T16 description functional 19 general 3 pin 5 E EPROM selectable options 58 expanded register file 20 expanded register file architecture 22 expanded register ...
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L low-voltage detection register 58 M memory, program 19 modulo-N mode T16_OUT 41 T8_OUT 37 O oscillator configuration 47 output circuit, counter/timer 43 P package information 20-pin DIP package diagram 85 20-pin SSOP package diagram 86 28-pin DIP package diagram ...
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SMR2(F)0Dh 34 stack pointer high 73 stack pointer low 73 stop mode recovery 50 stop mode recovery 2 55 stop-mode recovery 66 stop-mode recovery 2 67 T16 control 63 T8 and T16 common control functions 62 T8/T16 control 63 TC16H(D)07h ...
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XTAL1 pin function 10 XTAL2 5 XTAL2 pin function 10 PS023807-0707 Product Specification 102 Index ...
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... For answers to technical questions about the product, documentation, or any other issues with Zilog’s offerings, please visit Zilog’s Knowledge Base at http://www.zilog.com/kb. For any comments, detail technical questions, or reporting problems, please visit Zilog’s Technical Support at http://support.zilog.com. PS023807-0707 ZGP323H ...