ZGP323HAP4016G Zilog, ZGP323HAP4016G Datasheet - Page 64

• Manufacturer Part Number: ZGP323HAP4016G
• Description: IC Z8 GP MCU 16K OTP 40DIP
• Manufacturer: Zilog
• Series: Z8® GP™r

Specifications of ZGP323HAP4016G

• Core Processor: Z8
• Core Size: 8-Bit
• Speed: 8MHz
• Peripherals: HLVD, POR, WDT
• Number Of I /o: 32
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: OTP
• Ram Size: 237 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 40-DIP (0.620", 15.75mm)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Connectivity: -
• Other names: 269-4330; ZGP323HAP4016G

Expanded Register File Control Registers (0D)
PS023807-0707
Note:
Note:
Do not modify register P01M while checking a low-voltage condition. Switching noise of
both ports 0 and 1 together might trigger the LVD flag.
Voltage Detection and Flags
The Voltage Detection register (LVD, register 0CH at the expanded register bank 0Dh)
offers an option of monitoring the V
0 of LVD register is set. Once Voltage Detection is enabled, the V
real time. The flags in the LVD register valid 20 uS after Voltage Detection is enabled. The
HVD flag (bit 2 of the LVD register) is set only if V
(bit 1 of the LVD register) is set only if V
tion is enabled, the LVD flag also triggers IRQ5. The IRQ bit 5 latches the low-voltage
condition until it is cleared by instructions or reset. The IRQ5 interrupt is served if it is
enabled in the IMR register. Otherwise, bit 5 of IRQ register is latched as a flag only.
If it is necessary to receive an LVD interrupt upon power-up at an operating voltage lower
than the low battery detect threshold, enable interrupts using the Enable Interrupt instruc-
tion (EI) prior to enabling the voltage detection.
The expanded register file control registers (0D) are depicted in
Figure
Field
LVD
*
Default after POR.
41.
Bit Position
76543---
-----2--
------1-
-------0
R
R
R/W
1
0*
1
0*
1
0*
CC
voltage. The Voltage Detection is enabled when bit
Reserved
CC
Description
No Effect
HVD flag set
HVD flag reset
LVD flag set
LVD flag reset
Enable VD
Disable VD
is lower than the V
CC
is higher than V
LVD
Figure 37
Product Specification
CC
. When Voltage Detec-
level is monitored in
Functional Description
HVD.
through
The LVD flag
ZGP323H
59