ZGP323HSP2004G Zilog, ZGP323HSP2004G Datasheet - Page 27

IC Z8 GP MCU 4K OTP 20DIP

ZGP323HSP2004G

Manufacturer Part Number
ZGP323HSP2004G
Description
IC Z8 GP MCU 4K OTP 20DIP
Manufacturer
Zilog
Series
Z8® GP™r
Datasheets

Specifications of ZGP323HSP2004G

Core Processor
Z8
Core Size
8-Bit
Speed
8MHz
Peripherals
HLVD, POR, WDT
Number Of I /o
16
Program Memory Size
4KB (4K x 8)
Program Memory Type
OTP
Ram Size
237 x 8
Voltage - Supply (vcc/vdd)
2 V ~ 5.5 V
Oscillator Type
Internal
Operating Temperature
0°C ~ 70°C
Package / Case
20-DIP (0.300", 7.62mm)
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Data Converters
-
Connectivity
-
Other names
269-4384
ZGP323HSP2004G
PS023807-0707
↑↑↑↑↑ Bits 5,4,3,2,1 not reset with a Stop Mode Recovery
↑↑↑↑ Bits 5 and 4 not reset with a Stop Mode Recovery
↑↑↑ Bits 5,4,3,2 not reset with a Stop Mode Recovery
↑↑ Bit 5 Is not reset with a Stop Mode Recovery
** All addresses are in hexadecimal
U = Unknown
↑ Is not reset with a Stop Mode Recovery, except Bit 0
* Is not reset with a Stop Mode Recovery
*
Working Register
Group Pointer
(0) 03 P3
(0) 02 P2
(0) 01 P1
(0) 00 P0
Expanded Reg. Bank 0/Group (0)
FF
F0
7F
0F
00
7 6 5 4 3 2 1 0
Register Pointer
Figure 13. Expanded Register File Architecture
Register File (Bank 0)**
0
Z8 Standard Control Registers
U
U
U
Expanded Register
Bank Pointer
U
Expanded Reg. Bank 0/Group 15**
Expanded Reg. Bank F/Group 0**
Expanded Reg. Bank D/Group 0
↑↑↑↑↑
↑↑↑↑
↑↑↑
↑↑
*
*
*
*
*
*
*
*
*
*
*
*
*
FF
FE
FD
FC
FB
FA
F9
F8
F7
F6
F5
F4
F3
F2
F1
F0
(F) 0F WDTMR
(F) 0E Reserved
(F) 0D SMR2
(F) 0C Reserved
(F) 0B SMR
(F) 0A Reserved
(F) 09 Reserved
(F) 08 Reserved
(F) 07 Reserved
(F) 06 Reserved
(F) 05 Reserved
(F) 04 Reserved
(F) 03 Reserved
(F) 02 Reserved
(F) 01 Reserved
(F) 00 PCON
(D) 0C
(D) 0B
(D) 0A
(D) 09
(D) 08
(D) 07
(D) 06
(D) 05
(D) 04
(D) 03
(D) 02
(D) 01
(D) 00
IPR
P01M
P3M
P2M
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
SPL
SPH
RP
FLAGS
IMR
IRQ
CTR3
HI16
LO16
TC16H
TC16L
TC8H
TC8L
CTR2
CTR1
CTR0
LVD
HI8
LO8
Product Specification
D7 D6 D5 D4 D3 D2 D1 D0
U U U U U U U U
U U U U U U U U
0 0 0 0 0 0 0 0
U U U U U U U U
U U U U U U U U
0 0 0 0 0 0 0 0
U U U U U U U U
1 1 0 0 1 1 1 1
0 0 0 0 0 0 0 0
1 1 1 1 1 1 1 1
U U U U U U U U
U U U U U U U U
U U U U U U U U
U U U U U U U U
U U U U U U U U
U U U U U U U U
U U 0 0 1 1 0 1
U 0 1 0 0 0 U 0
1 1 1 1 1 1 1 0
0 0 0 0 0 0 0 0
U U U U U U U 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 1 1 1 1 1
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
Functional Description
Reset Condition
ZGP323H
22

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