ZLF645E0H2864G Zilog, ZLF645E0H2864G Datasheet - Page 144

• Manufacturer Part Number: ZLF645E0H2864G
• Description: IC MCU 64K FLASH 1K RAM 28-SSOP
• Manufacturer: Zilog
• Series: Crimzon™ ZLFr

Specifications of ZLF645E0H2864G

• Core Processor: Z8 LXMC
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: UART/USART
• Peripherals: Brown-out Detect/Reset, HLVD, POR, WDT
• Number Of I /o: 24
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 1.9 V ~ 3.6 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 28-SSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Oscillator Type: -
• Other names: 269-4719

PS026407-0408
Bit Position
[1]
[0]
Power-On Reset Timer
Watchdog Timer
Caution:
When power is initially applied to the device, a timer circuit clocked by a dedicated
on-board RC-oscillator provides the POR timer function. The POR timer circuit is a one-
shot timer that keeps the internal reset signal asserted long enough for V
oscillator circuit to stabilize before instruction execution begins.
The reset timer is triggered by one the following conditions:
•
•
•
SMR[5] can be cleared to 0 to bypass the POR timer on a Stop Mode Recovery. This must
only be done when using an external clock that does not require a startup delay.
The Watchdog Timer (WDT) is a retriggerable one-shot timer that resets the Z8 LXMC
CPU if it reaches its terminal count. The WDT must initially be enabled by executing the
WDT instruction. On subsequent executions of the WDT instruction, the WDT is
refreshed. The WDT circuit is driven by an on-board RC-oscillator. The WDT instruction
affects the Zero (Z), Sign (S), and Overflow (V) flags.
The POR clock source is an internal RC-oscillator. Bits 0 and 1 of the WDT register
control a tap circuit that determines the minimum time-out period. Bit 2 determines
whether the WDT is active during HALT, and bit 3 determines WDT activity during STOP
mode. Bits 4 through 7 are reserved (see
only during the first 60 processor cycles (120 XTAL clocks) from the execution of the first
instruction after power-on reset, watchdog timer Reset, or a Stop Mode Recovery (see
Stop Mode
Value
Failure of an application to provide a stable oscillating clock input to XTAL1 before the
end of the ZLF645’s POR period may result in an indeterminate chip behavior and must
be avoided. For details on the POR timing range, see
Electrical Characteristics
Initial power-on or recovery from a VBO/standby condition.
Stop Mode Recovery (if register bit SMR[5] = 1)
Watchdog Timer time-out.
0
1
0
1
Description
LVD clear.
Low-voltage detected (V
Voltage detection disabled.
Voltage detection enabled.
Recovery). After this point, the register cannot be modified by any means. The
chapter.
DD
<V
Table 69
LVD)
on page 137). This register is accessible
ZLF645 Series Flash MCUs
Table 82
Product Specification
Power-On Reset Timer
on page 164 in the
DD
and the
Fast
136