ZLF645E0H2864G Zilog, ZLF645E0H2864G Datasheet - Page 79

• Manufacturer Part Number: ZLF645E0H2864G
• Description: IC MCU 64K FLASH 1K RAM 28-SSOP
• Manufacturer: Zilog
• Series: Crimzon™ ZLFr

Specifications of ZLF645E0H2864G

• Core Processor: Z8 LXMC
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: UART/USART
• Peripherals: Brown-out Detect/Reset, HLVD, POR, WDT
• Number Of I /o: 24
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 1.9 V ~ 3.6 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 28-SSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Oscillator Type: -
• Other names: 269-4719

Flash Control Register Definitions
Table 34. Flash Control Register (FCTL)
PS026407-0408
Bit Position
[7:0]
Bits
Field
Reset
R/W
Address
Flash Control Register
W
7
0
The Flash Controller must be unlocked using the Flash Control register (see
before programming or erasing the Flash memory. Writing
Flash Control register unlocks the Flash Controller. When the Flash Controller is
unlocked, the Flash memory can be enabled for Mass Erase or Page Erase by writing the
appropriate enable command to the FCTL. Page Erase applies only to the active page
selected in Flash Page Select register. Mass Erase is enabled only through the ICP. Writing
an invalid value or an invalid sequence returns the Flash Controller to its locked state. The
Write-only Flash Control register shares its Register File address with the Read-only Flash
Status register.
Value
8CH
5EH
73H
95H
63H
W
6
0
Description
FCMD — Flash Command
First unlock command.
Second unlock command.
Page Erase command (must be third command in sequence to initiate
Page Erase).
Mass Erase command (must be third command in sequence to initiate
Mass Erase).
Enable Flash Sector Protect Register Access.
W
5
0
Bank F, Register address: 01H
W
4
0
FCMD
W
3
0
ZLF645 Series Flash MCUs
W
2
0
Flash Control Register Definitions
73H 8CH
Product Specification
, sequentially, to the
W
1
0
Table
W
0
0
34)
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